Semiconductor Pattern Formation via Selective Spacer Removal
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in efficiently forming patterns with varying widths and spacings using self-aligned reverse patterning, which requires multiple steps and can be complex due to the need for precise etching and spacer management.
Innovation Solution
The method involves simultaneously forming multiple patterns with different widths by using first and second spacers with voids and structures between them, allowing for the creation of mask patterns with varying sizes by maintaining or removing structures between sidewall spacers in different regions of the chip, thereby defining elements with distinct dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned reverse patterning is used to form patterns with varying widths and spacings, then manufacturing precision is improved, but device complexity and processing steps increase
Solution Approach 1:
The patent divides the feature layer into multiple segments (first feature layer and second feature layer) with different spacings. By forming spacers on each segment separately and using selective removal, the method creates different pattern widths in different regions without requiring a single complex multi-step process for the entire structure.
Solution Approach 2:
The patent applies different spacer configurations to different regions: first spacers with voids between them for one region, and second spacers with structures between them for another region. This local differentiation allows each region to have optimized pattern dimensions while using the same overall spacer-based approach.
2Productivity
If multiple spacers are used to form different pattern widths simultaneously, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The spacers are formed through self-aligned processes where the spacer material conformally deposits on the feature layer structures. This self-alignment mechanism automatically ensures precise spacing between patterns without requiring external alignment steps, maintaining high precision while enabling simultaneous formation of multiple patterns.
Solution Approach 2:
The patent performs preliminary formation of the feature layer with specific spacings before depositing the spacer material. This preliminary structuring establishes the foundation for subsequent spacer formation, ensuring that the final pattern dimensions are controlled by the initial feature layer geometry rather than requiring precise control during spacer deposition.
3Adaptability or versatility
If structures are selectively removed from certain regions, then adaptability is improved, but loss of substance increases
Solution Approach 1:
The patent selectively removes the feature layer structure from specific regions after spacers have been formed. By extracting only the necessary portions (first feature layer in first region, second feature layer in second region), the method achieves region-specific pattern control while minimizing unnecessary material removal.
Data Source
AI summary
Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.