Semiconductor Patterning with Etching Buffer Layer
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Solution Overview
Problem
The SADP process faces challenges in controlling the thickness and uniformity of material layers due to pattern density differences between dense and sparse regions in DRAM devices, leading to deformation and residues.
Innovation Solution
A method involving a hard mask layer, multiple material layers, and an etching back process is used to form structures on a semiconductor substrate, where a third material layer acts as an etching buffer to compensate for thickness variations, preventing over-etching and maintaining pattern integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SADP process is used to form dense array patterns, then pattern density is improved, but material layer thickness uniformity deteriorates due to loading effect from pattern density differences
Solution Approach 1:
The patent applies local quality by forming a third material layer selectively on the second material layer in the peripheral region (sparse pattern area) to compensate for thickness differences. This creates different local structures: the dense array region has only the second material layer while the peripheral region has an additional third material layer, thereby equalizing the overall thickness and etching load across different pattern density regions.
Solution Approach 2:
The third material layer is formed in advance before the etching process to pre-compensate for the thickness difference caused by the loading effect. This preliminary action ensures that when etching occurs, both the array region and peripheral region have equivalent total thickness, preventing over-etching in the peripheral region and maintaining pattern integrity.
2Manufacturing precision
If material layer thickness is reduced to compensate for loading effect, then etching precision is improved, but pattern deformation occurs due to insufficient thickness
Solution Approach 1:
Instead of uniformly reducing material layer thickness across the entire substrate, the patent applies local quality by selectively adding a third material layer only in the peripheral region. This maintains sufficient total thickness in both regions: the array region keeps its original second material layer thickness for pattern integrity, while the peripheral region gains additional thickness to match, thereby preventing both over-etching and under-thickness issues simultaneously.
3Manufacturing precision
If uniform material layer thickness is maintained across dense and sparse regions, then etching uniformity is improved, but loading effect from pattern density differences cannot be compensated
Solution Approach 1:
The patent changes the structural parameter of the material layer configuration by adding a third material layer selectively in the peripheral region. This parameter change transforms the thickness distribution from non-uniform (causing loading effects) to effectively uniform during etching, as the additional layer compensates for the lower etching load in the sparse peripheral region, achieving etching uniformity across different pattern density areas.
Data Source
AI summary
A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.