Semiconductor Patterning for Critical Dimension Uniformity
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Solution Overview
Problem
As semiconductor technology advances, critical dimension (CD) variations and uniformity issues arise due to variations in pattern density across different regions of semiconductor wafers, particularly as feature sizes decrease, affecting the fidelity of mask features in underlying material layers.
Innovation Solution
A method involving multiple selective etch processes and patterning layers, including a protector layer and hard mask layers, is employed to achieve improved CD uniformity by forming specific openings and patterns in the hard mask layers to accurately expose and etch device layers, using photolithography and etching techniques to create precise patterns and openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size decreases to advance semiconductor technology nodes, then device functionality and integration density improve, but critical dimension uniformity and pattern fidelity deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple distinct stages: forming a mandrel pattern, depositing spacers, selectively removing portions, and repeating the process. This multi-stage segmentation allows each step to be optimized independently, achieving the required CD uniformity at advanced nodes while maintaining high integration density
Solution Approach 2:
The patent employs preliminary action through the formation of mandrels and spacers before final pattern transfer. The mandrel structures are created first, followed by spacer deposition that defines the final critical dimensions. This preliminary structuring enables precise CD control before the actual device layer patterning occurs
2Manufacturing precision
If multiple selective etch processes and patterning layers are used to improve CD uniformity, then pattern fidelity improves, but process complexity increases
Solution Approach 1:
The patent applies universality by designing the mandrel and spacer structures to serve multiple functions: they act as etch masks, define critical dimensions, and provide mechanical support during processing. This multi-functionality reduces the need for separate dedicated structures, thereby managing process complexity while achieving high CD uniformity
Solution Approach 2:
The patent uses intermediary materials such as spacer layers and mandrel structures that mediate between the photolithography pattern and the final device layer. These intermediaries enable precise pattern transfer by providing a controlled interface for etching, improving CD uniformity without requiring direct photolithographic patterning of the device layer itself
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances critical dimension uniformity and fidelity of pattern transfer, improving the replication of small features in semiconductor devices, addressing the challenges of CD variations and uniformity at advanced technology nodes.
Implementation Method 1
using photolithography and etching techniques to create precise patterns and openings
Implementation Method 2
The first portion of the protector layer and the first portion of the hard mask layer are exposed to a first selective etch to form a first hard mask layer opening
Data Source
AI summary
Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.