Semiconductor Patterning Structure for Smaller Critical Dimensions
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in reducing critical dimensions of integrated circuit lines and via interconnects due to limitations in photolithography and the quality issues with conformal layers used to reduce dimensions.
Innovation Solution
The proposed semiconductor device structure includes a first conductive layer, a dielectric layer, an energy-removable layer, and a patterned mask with specific patterns in dense and loose regions. The energy-removable layer is conformally deposited and processed to allow for the formation of a second pattern on the sidewalls of the first pattern, reducing the critical dimension without requiring new photolithographic techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography is used to pattern ICs, then manufacturing capability is maintained, but minimum pitch constraints limit feature size reduction
Solution Approach 1:
The patent segments the patterning process into multiple steps: first forming initial patterns using conventional photolithography, then using self-aligned multiple patterning (SAMP) to further divide and reduce the critical dimensions. This allows achieving smaller features without requiring new lithography tools with higher resolution capabilities.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structures by forming mandrels, depositing conformal layers, and creating vias. This dimensional transition enables further feature size reduction through self-aligned processes that exploit vertical stacking rather than relying solely on lateral resolution improvement.
2Manufacturing precision
If conformal layers are deposited using ALD to reduce critical dimensions, then CD reduction is achieved, but material quality deteriorates with low density and poor mechanical strength
Solution Approach 1:
The patent changes the deposition parameters and material composition by using CVD processes with optimized temperature, pressure, and gas flow conditions to deposit high-quality silicon oxide and silicon nitride layers. This produces dense, mechanically strong films that maintain excellent adhesion while achieving the required critical dimension reduction, avoiding the material quality issues associated with standard ALD processes.
3Manufacturing precision
If ALD oxide layers are deposited to reduce critical dimensions, then CD control is improved, but adhesion and chemical compatibility deteriorate causing delamination
Solution Approach 1:
The patent optimizes deposition parameters including temperature, pressure, and gas composition to produce oxide layers with improved adhesion properties. The CVD process parameters are specifically tuned to create films with better chemical compatibility and bonding to underlying layers, preventing delamination while maintaining critical dimension control.
Solution Approach 2:
The patent employs composite material structures with multiple conformal layers of different materials (silicon oxide, silicon nitride) deposited in sequence. Each layer is engineered with specific properties to provide adhesion, mechanical strength, and chemical compatibility, creating a composite structure that overcomes the limitations of single-material approaches.
4Ease of manufacture
If wet-clean process is used to remove oxide materials, then material removal is achieved, but CD loss and undercut issues occur
Solution Approach 1:
The patent replaces the wet chemical cleaning process with a dry plasma-based removal process. The plasma etching method provides anisotropic removal that maintains vertical sidewalls and prevents undercutting, thereby preserving critical dimensions while effectively removing the oxide sacrificial layers. This substitution of chemical-mechanical wet cleaning with a controlled plasma process eliminates the CD loss and undercut issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the critical dimension of semiconductor device features, enhancing performance and reducing manufacturing costs by avoiding the need for new, costly photolithographic tools.
Implementation Method 1
an energy-removable layer conformally deposited over the first dielectric layer
Implementation Method 2
conformally deposited
Implementation Method 3
a second pattern with a smaller critical dimension is formed on the sidewalls of the first pattern using thermal oxidation
Data Source
AI summary
The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.