Semiconductor Patterning Using Line Pattern Masks

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Solution Overview

Problem

Conventional lithography techniques struggle to achieve smaller pattern pitches and maintain critical dimension uniformity, often resulting in misalignment due to the complexity of fabrication processes.

Innovation Solution

A patterning method involving multiple hard mask layers and mask layers is used to form a patterned material layer with aligned holes, where line pattern masks are used to divide holes into smaller sections, allowing for precise control over critical dimensions and pitch, and adjusting the dimensions of these masks to achieve smaller pattern pitches and improved alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lithography techniques are used, then the fabrication process is simple, but the pattern pitch cannot be smaller than about 76 nm and misalignment occurs

Engineering Contradiction:
Improvepattern pitchVSAvoidfabrication process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is divided into multiple sequential steps: forming a first mesh hard mask layer with first holes, forming a second mesh hard mask layer with second holes, and performing multiple etching steps. This segmentation allows achieving smaller pattern pitches (below 76 nm) by breaking down the complex patterning into manageable stages, with each step contributing to the final precise pattern geometry

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs preliminary actions by pre-forming the first mesh hard mask layer with controlled first holes before subsequent patterning steps. The critical dimension of first holes in a first direction is made greater than in a second direction, preparing the structure for anisotropic etching and enabling precise control of the final pattern dimensions while maintaining alignment

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If secondary lithography and etching processes are used to achieve smaller pitch, then the pattern pitch can be reduced, but misalignment occurs and critical dimension uniformity becomes hard to control

Engineering Contradiction:
Improvepattern pitchVSAvoidalignment accuracy
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The method uses two different mesh hard mask layers (first and second) with different hole geometries and orientations. The first mesh hard mask layer has first holes with critical dimension in first direction greater than in second direction, while the second mesh hard mask layer has second holes with critical dimension in second direction greater than in first direction. This equipotential approach ensures that etching from different directions produces consistent final pattern dimensions, eliminating misalignment issues

Inventive Principle:
Principle #12Equipotentiality

Solution Approach 2:

The invention changes the parameters of the mask layers by controlling the critical dimensions of first holes and second holes in different directions. By making the critical dimension of first holes in the first direction greater than in the second direction, and vice versa for second holes, the method achieves isotropic etching results from anisotropic masks, ensuring uniform critical dimension and perfect alignment

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If multiple hard mask layers and etching steps are used, then smaller critical dimension can be achieved, but the fabrication complexity increases

Engineering Contradiction:
Improvecritical dimensionVSAvoidfabrication process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The method employs nested doll principle by forming the second mesh hard mask layer on top of the first mesh hard mask layer structure. The first etching step creates patterns through the second hard mask layer, and the second etching step further patterns the first hard mask layer and material layer. This nested arrangement allows achieving smaller critical dimensions through multiple levels of patterning control

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The first mesh hard mask layer is formed in advance with specific hole geometries (critical dimension in first direction greater than in second direction) to prepare the structure for subsequent anisotropic etching. This preliminary action enables precise control of the final critical dimension while streamlining the overall fabrication process

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces pattern pitch and enhances critical dimension uniformity by aligning patterns and adjusting mask dimensions, overcoming misalignment issues and improving the uniformity of critical dimensions in semiconductor structures.

Implementation Method 1

The second hard mask layer is etched with the first mask layer as an etching mask to form a patterned second hard mask layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS9412615B2Patterning method and semiconductor structure including forming a plurality of holes using line pattern masks
Publication Date: 2016.08.09 MACRONIX INTERNATIONAL CO LTD
  • US9412615B2 patent drawing
  • US9412615B2 patent drawing
  • US9412615B2 patent drawing

AI summary

A patterning method is provided. A substrate including a material layer thereon is provided. A patterned hard mask layer, having a plurality of first holes, is formed on the material layer. Afterward, a mask layer, including a plurality of line pattern masks extending in a direction and dividing each first hole into a second hole and a third hole, is formed. The material layer is patterned using the patterned hard mask layer and the mask layer as masks to form a patterned material layer having a plurality of fourth and fifth holes. Furthermore, a semiconductor structure is provided.