Semiconductor Patterning Using Multi-Step Masking for Sub-Critical Dimensions
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Solution Overview
Problem
Current photolithographic processes are limited by minimum achievable feature sizes and gap widths, which hinder the production of smaller semiconductor structures, particularly in transistor gate channels, leading to increased power consumption and reduced performance due to high-temperature oxidation processes and high costs associated with advanced photolithographic techniques.
Innovation Solution
A method involving multiple photolithographic patterning steps with positive and negative ramp angles applied to mask layers, allowing for the reduction of structure sizes below the critical dimensions, enabling the production of semiconductor components with feature sizes smaller than those achievable by standard photolithographic systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard photolithographic processes are used, then manufacturing costs are controlled, but minimum achievable feature sizes and gap widths are limited
Solution Approach 1:
The patent divides the single photolithographic patterning process into multiple sequential patterning steps. Each step creates features at different locations on the substrate, allowing the cumulative effect to achieve smaller effective feature sizes and gap widths than any single step could produce alone, while using existing photolithographic equipment
Solution Approach 2:
The patent introduces a temporal dimension by performing multiple patterning steps sequentially rather than attempting to create all features in a single step. This multi-step temporal approach enables achieving sub-critical dimensions that would be impossible in a single spatial patterning operation
2Use of energy by moving object
If gate channel length is reduced, then power consumption decreases and clock rate increases, but minimum achievable feature size limits further reduction
Solution Approach 1:
The gate channel patterning is divided into multiple photolithographic steps, each creating portions of the final gate structure. This segmentation allows the effective gate channel length to be reduced beyond the critical dimension limit of single-step photolithography, enabling lower power consumption and higher clock rates
3Manufacturing precision
If high-temperature oxidation process is used to produce oxide spacer, then gate structures are formed, but transistor performance is detrimentally affected
Solution Approach 1:
The patent changes the process parameters by using multiple photolithographic patterning steps with varying exposure conditions and developing processes. This allows precise control of feature formation without requiring high-temperature oxidation, thereby maintaining transistor performance while achieving the necessary gate structure formation
4Manufacturing precision
If advanced photolithographic process is used to achieve smaller structures, then feature size is reduced, but significant additional cost outlay is required
Solution Approach 1:
Instead of investing in expensive advanced photolithographic equipment, the patent segments the patterning process into multiple steps using existing equipment. This approach achieves smaller effective feature sizes through process decomposition rather than through costly hardware upgrades
Solution Approach 2:
The patent applies multiple photolithographic patterning steps, where each step creates partial features that are completed in subsequent steps. This excessive action of applying more steps than a conventional single-step process enables achieving smaller dimensions without requiring more advanced (and expensive) single-step equipment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of semiconductor structures with feature sizes and gap widths below the minimum critical dimensions, reducing power consumption and improving transistor performance while minimizing costs by achieving smaller gate channel lengths and tighter gate spacings.
Implementation Method 1
structures are projected onto a photosensitive layer by means of a photolithographic stepper or scanner
Data Source
AI summary
A method for producing semiconductor components on a substrate including photolithographic patterning steps, in which method, on the substrate, a first layer to be patterned is applied and a second layer serving as a mask layer for the first layer to be patterned is applied, wherein a third layer serving as a mask for the second layer is applied, and wherein at least two photolithographic patterning processes are carried out successively for the second layer, wherein, during one of the patterning processes, after the production of a structure made from a photosensitive layer for the provision of a mask layer for a patterning process at the third layer, positive ramp angles α are produced at the patterning edges of the third layer, as a result of which the structures remaining free, given a thickness h of the third layer, decrease in size by a value D=2*h/tan α.