Semiconductor Patterning via Multi-Step Mask Transfer
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Solution Overview
Problem
Current semiconductor manufacturing technologies face difficulties in reducing line/space width to less than 50 nm/50 nm without replacing existing machines, which is costly and limits resolution beyond 65 nm in photolithography processes.
Innovation Solution
A method involving multiple pattern transfer processes with different hard masks and two photolithography steps using patterned photoresist layers with alternating patterns, allowing for the formation of a semiconductor structure with a line/space width of less than 50 nm/50 nm using existing equipment, by sequentially forming and patterning mask layers with specific etch selectivities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing photolithography machines and processes are used, then manufacturing cost is reduced, but line/space width cannot be reduced to less than 50 nm/50 nm
Solution Approach 1:
The patent divides the single photolithography patterning process into multiple sequential patterning steps. First, a preliminary pattern is formed, then additional patterns are formed in the spaces between existing patterns using separate photolithography and etching steps. This segmentation allows achieving sub-50 nm resolution with existing equipment by breaking down the complex patterning task into manageable stages.
Solution Approach 2:
The patent performs preliminary patterning to create a first set of patterns before forming the final patterns. The preliminary patterns serve as a foundation that enables subsequent patterning steps to achieve the desired sub-50 nm line/space width. This preliminary action prepares the substrate in a state that facilitates the formation of finer features using existing photolithography capabilities.
2Manufacturing precision
If new machines with shorter wavelength light sources are used, then line/space width of less than 50 nm/50 nm can be achieved, but manufacturing cost increases significantly
Solution Approach 1:
Instead of replacing machines, the patent segments the patterning process into multiple steps that can be performed with existing equipment. The first step creates preliminary patterns, and subsequent steps create additional patterns in the interstitial spaces, effectively achieving fine pitch without requiring shorter wavelength lithography tools.
Solution Approach 2:
The patent transitions from a single-plane patterning approach to a multi-step sequential patterning approach. By adding the dimension of time (multiple sequential steps) rather than upgrading the optical resolution in a single step, the process achieves sub-50 nm features using existing machine capabilities.
3Manufacturing precision
If photolithography resolution limits are exceeded, then critical dimension beyond 65 nm cannot be fabricated, but process capability is insufficient
Solution Approach 1:
The patent overcomes photolithography resolution limits by segmenting the critical dimension formation into multiple patterning steps. The first step establishes a preliminary pattern structure, and subsequent steps add additional patterns with finer spacing in the spaces between preliminary patterns, effectively achieving critical dimensions below the single-step photolithography resolution limit.
Solution Approach 2:
The patent uses preliminary patterning to create a structured foundation that enables subsequent finer patterning. The preliminary patterns are intentionally designed to leave spaces that will be filled in later steps, allowing the process to achieve critical dimensions that exceed the capabilities of a single photolithography exposure step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with reduced line/space width without replacing existing machinery, significantly lowering costs and improving competitiveness by achieving critical dimensions beyond photolithography resolution limits.
Implementation Method 1
a patterned photoresist layer is formed on the BARC layer, wherein the patterns of the patterned photoresist layer and the patterns of the first pattern transfer layer are alternately arranged. Afterwards, the BARC layer is patterned, using the patterned photoresist layer as a mask
Implementation Method 2
the etch selectivity of the first mask layer to the second mask layer is greater than about 10, for example. According to an embodiment of the present invention, the etch selectivity of the second mask layer to the first pattern transfer layer is greater than about 5, for example.
Data Source
AI summary
A method of forming a semiconductor structure is provided. First, a target layer and a mask layer are sequentially formed on a substrate. Thereafter, a first pattern transfer layer having a plurality of openings is formed on the mask layer. Afterwards, a second pattern transfer layer is formed in the openings of the first pattern transfer layer. The mask layer is then patterned, using the first pattern transfer layer and the second pattern transfer layer as a mask, so as to form a patterned mask layer. Further, the target layer is patterned using the patterned mask layer.