Semiconductor Patterning Using SiARC and Spacer Assist Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The conventional sidewall image transfer (SIT) patterning process in semiconductor manufacturing faces challenges with poor metal hard mask etching profiles due to inadvertent etching of low temperature silicon dioxide (LTO) spacers and high deposition temperatures required for silicon nitride (SiN) spacers, leading to reduced yield and reliability of semiconductor devices.
Innovation Solution
The method involves forming a wafer with a silicon anti-reflective coating (SiARC) layer and a spacer assist layer, where the SiARC layer has an etch rate similar to the spacer assist layer, allowing for simultaneous etching of these layers to maintain spacer height and prevent degradation, while using the remaining spacer and spacer assist layers as an etching mask to form a reliable hard mask profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If LTO is used as the spacer layer, then the deposition temperature is low, but the spacer height is reduced and side-profile is rounded due to inadvertent etching during SiARC etch back
Solution Approach 1:
The spacer structure is divided into two segments: an LTO spacer layer deposited at low temperature and a silicon nitride protection layer deposited at high temperature. This segmentation allows each layer to fulfill its specific function - the LTO layer provides the spacer function at low temperature while the silicon nitride layer protects it during subsequent etching processes.
Solution Approach 2:
The spacer structure uses a composite of two materials with different properties: LTO (low temperature silicon dioxide) and silicon nitride. The LTO provides low deposition temperature compatibility while the silicon nitride provides etch resistance during the SiARC etch back step, creating a composite structure that resolves the contradiction between low temperature deposition and etching protection.
2Reliability
If SiN is used as the spacer film, then etch selectivity is higher and spacer height is maintained, but deposition temperature exceeds 400 degrees causing degradation of the mandrel layer
Solution Approach 1:
The spacer function is segmented between two layers: the LTO layer provides the primary spacer structure at low temperature, while the thin silicon nitride layer provides the necessary etch protection. This segmentation allows the system to achieve high etch selectivity without requiring the main spacer layer to be deposited at high temperatures that would degrade the mandrel.
Solution Approach 2:
The LTO layer acts as an intermediary between the mandrel layer and the etching process. Instead of requiring the mandrel to withstand high temperature deposition, the LTO layer is deposited at low temperature and then protected by a thin silicon nitride layer during etching, mediating the interaction between the mandrel and the harsh etching conditions.
3Manufacturing precision
If the mandrel layer is made thicker to maintain spacer profile, then spacer height is sufficient, but the aspect ratio increases making OPL removal difficult
Solution Approach 1:
The invention changes the material composition parameter of the spacer structure by introducing a silicon nitride protection layer with superior etch resistance. This allows the LTO spacer layer to be thinner while still maintaining adequate profile during etching, thereby reducing the aspect ratio without sacrificing spacer height or profile quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains a stable spacer height, reduces aspect ratio, and prevents excess OPL removal, resulting in improved metal hard mask etching profiles, increased yield, and enhanced reliability of semiconductor devices.
Implementation Method 1
simultaneously etching the SiARC layer in a second region of the wafer and the exposed spacer assist layer in the first region of the wafer
Data Source
AI summary
A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The SiARC layer has an etch rate substantially similar to the etch rate of the spacer assist layer. The photoresist layer and the SiARC layer are removed from a first region to expose the spacer portions and the spacer assist layer. The SiARC layer in the second region and the exposed spacer assist layer in the first region are simultaneously etched leaving remaining spacer portions and remaining spacer assist layer portions. A part of the hard mask layer is etched to form hard mask portions in the first region using the remaining spacer portions and the remaining spacer assist layer portions as an etching mask.