Semiconductor Patterning Method Using Spacer Layers
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Solution Overview
Problem
Conventional dual patterning processes in semiconductor lithography are complex, time-consuming, and costly due to the need for multiple immersion lithography steps, which increases process time and expense.
Innovation Solution
A method involving sequential formation of layers on a substrate, including a bottom layer, hard mask layer, buffer mask layer, and mask layer, followed by patterning, etching, and deposition of sacrificial dielectric material and spacer layers to form columnar bodies and reduce pattern width and spacing, allowing for the use of a single photomask and fewer process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dual patterning process is used to achieve smaller line width, then manufacturing precision is improved, but device complexity and process time increase
Solution Approach 1:
The mask layer is divided into multiple layers (first mask layer, second mask layer, third mask layer) with different functions. The first mask layer defines initial patterns, the second mask layer creates columnar bodies, and the third mask layer forms final fine patterns. This segmentation allows each layer to be optimized for specific purposes, achieving smaller line widths without requiring multiple complete lithography cycles.
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional columnar structures. By forming columnar bodies with vertical sidewalls and using spacer layers deposited conformally on these vertical surfaces, the process achieves pattern scaling in the lateral dimension while utilizing the vertical dimension for process control, enabling finer features without proportional increases in process complexity.
2Manufacturing precision
If conventional dual patterning process is used to achieve smaller line width, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
Multiple patterning functions are merged into a single lithography exposure step. The first mask layer, second mask layer, and third mask layer are all patterned simultaneously in one exposure process, eliminating the need for multiple separate lithography cycles. This merging significantly reduces process time while maintaining the ability to achieve fine line widths through the multi-layer mask structure.
Solution Approach 2:
The first mask layer and second mask layer are formed and patterned in advance before the final patterning step. These preliminary layers establish the columnar body structures and spacer configurations that define the final pattern geometry, allowing the third mask layer to focus solely on creating the fine final patterns without requiring additional lithography cycles.
3Manufacturing precision
If conventional dual patterning process is used to achieve smaller line width, then manufacturing precision is improved, but product cost increases
Solution Approach 1:
The multi-layer mask structure serves multiple functions within a single process flow. The same lithography equipment and exposure tools used for conventional single-layer masking are utilized here, but the process achieves enhanced patterning capability through the additional mask layers. This multi-functionality allows existing equipment to produce finer features without requiring expensive new tooling or multiple specialized process lines.
Solution Approach 2:
The pattern from the photomask is copied multiple times through the different mask layers rather than requiring multiple photomasks and lithography cycles. The first, second, and third mask layers all receive the same or related pattern information from the photomask, creating a cascade of patterned structures that ultimately achieve the fine line width features without proportionally increasing photomask or lithography costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the patterning process, reduces pattern size and spacing, and lowers costs by eliminating the need for multiple immersion lithography steps, while improving process control and efficiency.
Implementation Method 1
depositing a spacer layer on the second columnar bodies
Implementation Method 2
depositing a spacer layer on the second columnar bodies
Implementation Method 3
etching the spacer layer to expose the hard mask layer under the second gaps
Data Source
AI summary
A method for forming fine patterns is described. A bottom layer, a hard mask layer, a buffer mask layer and a mask layer are sequentially formed on a substrate. The mask layer and the buffer mask layer are patterned to form first columnar bodies. The buffer mask layer is partially removed in the first columnar bodies and a sacrifice dielectric material is filled in the first gap between the first columnar bodies. The sacrifice dielectric material is patterned to form second columnar bodies. A conformal spacer layer is deposited on the second columnar bodies, and the conformal spacer layer forms spaced columnar body between the adjacent second columnar bodies. A second gap is formed between the spaced columnar body and the second columnar body. A core mask layer is formed in the second gaps. The mask layer and the sacrifice dielectric material are removed.