Semiconductor Layout Patterning With Spacer-Controlled Feature Spacing
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in accurately forming small features and preventing unwanted electrical connections due to the limitations of traditional photolithography, particularly when using multiple masks to create complex layouts, which can result in overlay errors and critical dimension issues.
Innovation Solution
The method involves decomposing a desired layout into sub-layouts and using multiple photomasks with spacer features to control the formation of additional features, ensuring precise spacing and independent control over feature widths and lengths, thereby avoiding electrical issues and improving pattern transfer accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography with multiple masks is used to create complex layouts, then the desired pattern can be transferred onto the wafer, but overlay errors and critical dimension issues occur resulting in unwanted electrical connections
Solution Approach 1:
The patent segments the layout decomposition process into distinct sub-layouts (first sub-layout and second sub-layout) that are formed at different stages. The first sub-layout features are formed initially, then a second sub-layout is formed that intentionally overlaps with the first. This segmentation allows independent control of each sub-layout's features, preventing overlay errors while achieving complex final patterns without unwanted electrical connections.
2Productivity
If feature sizes are decreased to increase device density, then more interconnected devices can be created per unit area, but the wavelength of light used in photolithography must also decrease creating additional difficulties
Solution Approach 1:
The patent divides the patterning process into multiple sequential steps with distinct sub-layouts, allowing each step to work at relaxed dimensions while achieving fine final features through the combination of overlaid sub-layouts. This avoids the need to directly pattern small features at their final dimensions in a single step, reducing photolithography process complexity.
Solution Approach 2:
The patent introduces an additional dimensional aspect by forming features in multiple layers (first sub-layout features and second sub-layout features at different positions), then combining them through overlap. This multi-dimensional approach allows achievement of small final feature sizes without requiring direct single-step patterning at those dimensions, thereby reducing process complexity.
3Adaptability or versatility
If multiple masks are used to form features of a single desired layout, then different features can be created, but adjacent features from different submasks may be formed too close resulting in unwanted electrical connections
Solution Approach 1:
The patent segments the feature formation into distinct sub-layouts with controlled spatial relationships. The first sub-layout and second sub-layout are formed independently with defined overlap regions, allowing versatile layout design while maintaining precise control over final feature spacing through the structured overlap approach, preventing unwanted electrical connections.
Solution Approach 2:
The patent uses the overlap region between first and second sub-layouts as an intermediary mechanism to control feature spacing. By defining how sub-layouts overlap and which features are formed from each, the method mediates between the need for layout versatility and precise spacing control, ensuring adjacent features maintain appropriate separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more precise control over feature formation, reducing the risk of unwanted connections and enhancing the reproducibility of small features by using spacers to manage the spacing and shape of additional features formed during the semiconductor fabrication process.
Implementation Method 1
Semiconductor fabrication relies heavily on the process of photolithography, in which light of a given frequency is used to transfer a desired pattern onto a wafer undergoing semiconductor processing. The photomask permits and prevents light in a desired layout onto a layer of the wafer, such as a photoresist (PR) mask, which chemically reacts to the light exposure
Data Source
AI summary
The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.