Semiconductor Patterning with Two-Step Etching for Critical Dimensions
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in achieving precise patterning and critical dimension formation due to the difficulty in scaling down feature sizes, leading to issues with lithography tools and patterning methods.
Innovation Solution
A two-step etching process is employed, where a first etchant with low selectivity is used to etch the oxide and underlayer, followed by a second etchant with high selectivity to etch the oxide and silicon-containing layer, ensuring complete removal of the oxide while avoiding over-etching of the silicon-containing layer, thereby defining a well-patterned underlayer and achieving the desired critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching process is used to remove oxide and etch silicon-containing layer, then the process is simple, but it is difficult to achieve precise critical dimension control and avoid over-etching
Solution Approach 1:
The etching process is divided into two distinct steps: first etching the oxide layer with a protective gas (O2) to remove oxide while minimizing silicon etching, then etching the silicon-containing layer with a reactive gas (CHF3) to achieve precise pattern transfer. This segmentation allows each step to be optimized for its specific function, resolving the contradiction between process simplicity and precision.
Solution Approach 2:
The oxide layer serves as an intermediary protective layer during the etching process. By maintaining the oxide layer during the first etching step and selectively removing it in the second step, the process achieves precise control over which materials are etched at each stage, enabling accurate critical dimension formation without over-etching.
2Manufacturing precision
If lithography tools and patterning methods are advanced to achieve smaller features, then critical dimension precision is improved, but process complexity and difficulty increase
Solution Approach 1:
The patent replaces complex lithography mechanical systems with a chemically-driven self-aligned etching approach. By using selective etching chemistry (O2 for oxide, CHF3 for silicon) and the oxide layer as a self-aligned mask, the process achieves precise patterning without requiring increasingly complex lithography tools, thus improving precision while avoiding increased process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise patterning of semiconductor devices by ensuring the oxide is completely removed without affecting the silicon-containing layer, resulting in accurate feature formation and meeting the required critical dimensions for semiconductor devices.
Implementation Method 1
etching the oxide and the underlayer with a first etchant, where a ratio of a first etching rate of the oxide and a second etching rate of the underlayer is about 1:1
Implementation Method 2
etching the oxide and the silicon-containing layer with a second etchant different from the first etchant to form a second opening below the first opening, where a third etching rate of the oxide is higher than a fourth etching rate of the silicon-containing layer
Data Source
AI summary
The disclosure provides a method of fabricating a semiconductor device, where the method includes the following operations. A semiconductor stack including a silicon-containing layer, an oxide deposited on a portion of the silicon-containing layer, an underlayer, and a resist layer is formed. The resist layer is patterned to form a first opening in the resist layer. The underlayer is etched to extend the first opening into the underlayer, where a top surface of the oxide is exposed by the first opening. The oxide and the underlayer are etched with a first etchant, where a ratio of etching rates of the oxide and the underlayer is about 1:1. The oxide and the silicon-containing layer are etched with a second etchant to form a second opening below the first opening, where an etching rate of the oxide is higher than that of the silicon-containing layer.