Semiconductor Optimization via Plackett-Burman and Genetic Algorithm
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of semiconductor characteristics in high-speed systems and diverse applications poses challenges in optimizing signal integrity within limited time frames, necessitating efficient experimental planning and evaluation condition optimization algorithms.
Innovation Solution
An electronic device and operating method that utilize a Plackett-Burman design (PBD) and genetic algorithm (GA) to optimize semiconductor characteristics. The device includes a PBD execution circuit for generating an initial design of experiment (DOE) set, a GA execution circuit for converting previous DOE sets into next generations, and a control circuit for managing the process and inputting experimental results into the GA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of evaluation cases is increased to achieve higher level optimization of semiconductor characteristics, then the optimization quality is improved, but the evaluation time period increases excessively
Solution Approach 1:
The patent applies preliminary action by using Plackett-Burman design to pre-select and screen the most influential parameters before conducting the main optimization experiment. This initial screening phase identifies key factors that have significant impact on semiconductor characteristics, allowing the subsequent genetic algorithm to focus only on these critical parameters rather than evaluating all possible parameters comprehensively. This two-stage approach (PBD screening + GA optimization) achieves high-level optimization quality while significantly reducing the total evaluation time period.
Solution Approach 2:
The patent segments the optimization process into two distinct phases: (1) Plackett-Burman design phase for parameter screening and identification of influential factors, and (2) Genetic algorithm phase for detailed optimization of the identified key parameters. This segmentation allows each phase to specialize in its specific task, with PBD efficiently filtering out non-critical parameters and GA performing deep optimization on the reduced set of key parameters, thereby achieving high optimization quality without requiring exhaustive evaluation of all parameters.
2Measurement precision
If comprehensive evaluation of semiconductor characteristics is performed, then the optimization accuracy is improved, but the complexity of experimental planning increases
Solution Approach 1:
The patent uses Plackett-Burman design as a preliminary action to screen and identify the most influential parameters before the main optimization process. This initial screening reduces the dimensionality of the problem by identifying only the key factors that significantly impact semiconductor characteristics, thereby simplifying the subsequent experimental planning while maintaining high optimization accuracy through focused evaluation of critical parameters using genetic algorithm.
3Reliability
If more setting values are evaluated to optimize signal integrity, then the signal integrity is improved, but the number of test cases increases excessively
Solution Approach 1:
The patent applies preliminary action by using Plackett-Burman design to pre-identify the most influential setting values that impact signal integrity. This screening phase evaluates a manageable number of test cases to determine which setting values have the greatest effect on signal integrity, allowing the subsequent genetic algorithm to focus optimization efforts only on these critical setting values rather than exhaustively testing all possible settings, thereby achieving high signal integrity with a reduced number of test cases.
Solution Approach 2:
The patent segments the evaluation of setting values into two phases: (1) PBD phase for screening and identifying influential setting values, and (2) GA phase for optimizing the identified key setting values. This segmentation reduces the total number of test cases required by focusing computational resources on the most impactful parameters, while still achieving comprehensive optimization of signal integrity through the iterative improvement process of the genetic algorithm applied to the reduced parameter set.
Data Source
AI summary
An electronic device includes a Plackett-Burman design (PBD) execution circuit, a genetic algorithm (GA) execution circuit, and a control circuit. The PBD execution circuit is configured to generate an initial design of experiment (DOE) set including a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device. The GA execution circuit is configured to convert a previous generation DOE set to a next generation DOE set. The control circuit is configured to transmit the initial DOE set to the external device, receive, from the external device, an initial characteristic evaluation, generate a starting DOE set based on the initial characteristic evaluation, and control a genetic algorithm to be performed with an experimental result of the starting DOE set as an input. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values influencing the semiconductor characteristics.