Semiconductor Integrated Circuit With Peeling And Stacking
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Solution Overview
Problem
Conventional methods for manufacturing semiconductor integrated circuits by stacking semiconductors are hindered by long production times, mechanical inflexibility, and defects due to the need for etching and polishing, which also generate dust and reduce productivity.
Innovation Solution
A method involving the formation of release layers on substrates, peeling off layers with semiconductor elements, and stacking them with overlapping openings to form through wirings, eliminating the need for etching and polishing, thereby improving productivity and mechanical flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through holes are formed by polishing the semiconductor substrate from its back surface, then integrated circuits are connected, but production time increases and productivity decreases
Solution Approach 1:
The invention forms openings in the semiconductor layer before stacking, rather than forming through holes in the substrate after stacking. This preliminary action eliminates the need for time-consuming polishing operations while ensuring proper alignment and connection of integrated circuits between substrates.
Solution Approach 2:
The invention divides the connection process into separate steps: forming openings in each substrate's semiconductor layer individually, then stacking the substrates. This segmentation eliminates the need for a single lengthy polishing operation to create through holes across the entire substrate thickness.
2Reliability
If through holes are formed by etching or polishing, then integrated circuits are connected, but dust is generated causing defects
Solution Approach 1:
Openings are formed in the semiconductor layer before substrate stacking, avoiding the need for subsequent polishing operations that generate dust. This preliminary formation of openings eliminates the source of dust contamination while maintaining effective circuit connection.
Solution Approach 2:
The invention extracts the harmful polishing step from the manufacturing process by forming openings in the semiconductor layer instead of creating through holes in the substrate through polishing. This removal of the polishing operation eliminates dust generation entirely.
3Adaptability or versatility
If semiconductor substrates are stacked to form integrated circuits, then high integration is achieved, but the structure becomes thick and mechanically inflexible
Solution Approach 1:
The invention uses thin film structures for the semiconductor layers and forms openings within these thin layers rather than creating thick through holes in rigid substrates. This approach maintains mechanical flexibility while achieving the necessary electrical connections for high integration.
Solution Approach 2:
The invention transitions from vertical through-hole connections in thick substrates to planar opening formations in thin semiconductor layers. This dimensional change in the connection approach reduces overall thickness while maintaining integration capability and improving mechanical flexibility.
Data Source
AI summary
A step of forming a through hole in a semiconductor substrate, or a step of polishing the semiconductor substrate from its back surface requires a very long time and causes decrease of productivity. In addition, when semiconductor substrates are stacked, a semiconductor integrated circuit which is formed of the stack is thick and has poor mechanical flexibility. A release layer is formed over each of a plurality of substrates, layers each having a semiconductor element and an opening for forming a through wiring are formed over each of the release layers. Then, layers each having the semiconductor element are peeled off from the substrates, and then overlapped and stacked, a conductive layer is formed in the opening, and the through wiring is formed; thus, a semiconductor integrated circuit is formed.