Semiconductor Penetration Electrodes in Outer Regions
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Solution Overview
Problem
Current High Bandwidth Memory (HBM) technologies face challenges in increasing input/output (I/O) channels and parallel processing due to limitations in reducing TSV size and pitch, leading to stress concentration and chip cracking during chip joining.
Innovation Solution
A semiconductor apparatus with laminated semiconductor chips and penetration electrodes that penetrate through the outer circumferential part of sub-memory arrays, distributed uniformly to reduce stress concentration and prevent cracking, allowing for increased I/O channels and parallel processing without the need for bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If TSV size is reduced and pitch is narrowed to increase I/O channels, then the number of input/output channels increases, but manufacturing precision requirements increase and stress concentration occurs
Solution Approach 1:
The patent segments the memory chip structure by dividing it into a central region and outer circumferential regions. Penetration electrodes are strategically placed only in the outer circumferential parts, separating the functional I/O regions from the stress-prone central joining region. This segmentation allows increased I/O channels in the outer regions without compromising the structural integrity of the central region.
Solution Approach 2:
The patent applies local quality by creating different structural characteristics in different regions of the chip. The outer circumferential parts contain penetration electrodes for I/O functions, while the central part is designed without penetration electrodes to handle joining stresses. This localized differentiation optimizes each region for its specific function while avoiding the trade-off between I/O density and manufacturing precision.
2Ease of manufacture
If large-size TSVs are arranged collectively at the central portion to simplify manufacturing, then manufacturing complexity is reduced, but stress concentration causes chip cracking
Solution Approach 1:
The patent extracts the penetration electrodes from the central portion where they would cause stress concentration during chip joining. By removing TSVs from the central region and placing them only in the outer circumferential parts, the design eliminates the stress concentration problem that leads to cracking, while still providing sufficient I/O channels through the distributed outer region electrodes.
3Reliability
If penetration electrodes are distributed in the outer circumferential part, then stress is uniformly distributed and cracking is prevented, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of penetration electrodes to a three-dimensional distributed arrangement in the outer circumferential regions. By utilizing the circumferential dimension around the chip perimeter, the design achieves uniform stress distribution across multiple distributed electrodes without requiring excessive precision in any single electrode's position, as the collective circular distribution naturally balances the stress.
Data Source
AI summary
A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; and a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips, wherein a semiconductor chip has at least one sub-memory array, and a penetration electrode penetrates through an outer circumferential part of the sub-memory array.