Semiconductor Penetration Electrodes for 3D Chip Stacking
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Solution Overview
Problem
Conventional three-dimensional semiconductor chip stacking methods using wire bonding result in long metal interconnect lengths, high interconnect density on the substrate, and increased production costs, with challenges in achieving fast transmission and microscopic bonding due to thermal expansion differences and complex manufacturing processes.
Innovation Solution
A method involving the formation of penetration electrodes in metal interconnect substrates and semiconductor chips, using laser beam machining to create through-holes in a resin substrate, applying metal plating, and inserting metal bumps for electrical connection at room temperature, reducing interconnect lengths and eliminating the need for high-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wire bonding is used for electrical connection between stacked semiconductor chips, then flexibility in routing wiring is improved, but metal interconnect lengths become very long and metal interconnect density on the mount substrate becomes very high
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional penetration electrodes that pass through the substrate thickness direction. This dimensional change allows direct vertical connections between upper and lower chips, eliminating the need for long lateral interconnects on the substrate, thereby reducing inductance and interconnect density while maintaining routing flexibility.
2Reliability
If penetration electrodes are formed by conventional methods, then electrical connection between chips is improved, but manufacturing complexity and cost increase due to additional process steps
Solution Approach 1:
The patent combines the penetration electrode formation process with the existing metal interconnect formation process. The same sputtering and electroplating steps used for creating metal interconnect layers are also used to form penetration electrodes, eliminating separate process steps and reducing manufacturing complexity while ensuring reliable electrical connections.
Solution Approach 2:
The metal interconnect formation process is designed to serve dual purposes: creating lateral metal interconnects for signal routing and forming vertical penetration electrodes for chip-to-chip connections. This multi-functionality reduces the number of dedicated process steps for penetration electrodes while maintaining connection reliability.
3Strength
If conventional bonding methods utilizing thermal energy are used, then bonding strength is improved, but bonding temperature must be high causing issues with thermal expansion differences between materials
Solution Approach 1:
The patent replaces thermal bonding mechanisms with mechanical pressure bonding. By applying sufficient pressure at room temperature or low temperature, the penetration electrodes achieve reliable mechanical and electrical contact with the metal interconnects, eliminating the need for high-temperature processing and avoiding thermal expansion mismatch issues between different materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable, low-cost electrical connections between chips and substrates with the shortest interconnect lengths, accommodating materials with different thermal expansion coefficients, and simplifies the manufacturing process by eliminating the need for heating, thus facilitating faster and more reliable bonding.
Implementation Method 1
forming through-holes in a resin substrate by laser beam machining
Implementation Method 2
applying a metal plating film to the sidewalls of the through-holes
Implementation Method 3
pressing a metal bump into contact with the through-holes to be inserted therein, due to a portion of the metal bump, undergoing deformation, causing the metal bumps to be geometrically caulked inside the respective through-holes
Data Source
AI summary
In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level, the method being a three-dimensional connection method very low in cost, and short in TAT in comparison with the known example, capable of bonding at an ordinary temperature, and excellent in connection reliability.