Semiconductor Performance Prediction From Partial Fabrication Data
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Solution Overview
Problem
The top-down optimization process for semiconductors is time-intensive, inefficient, and expensive, as it requires building and testing multiple devices to determine performance improvements.
Innovation Solution
A method that predicts the theoretical performance limits of fully fabricated semiconductor devices by measuring specific properties during the fabrication process and inputting them into device models, such as course, medium, and fine device models, to determine short circuit current density, current voltage relationships, and other performance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple devices are fabricated and tested to determine performance improvements, then reliable performance data is obtained, but time consumption and cost increase significantly
Solution Approach 1:
The patent measures semiconductor properties during the fabrication process itself, before the device is complete, and uses device models to predict final performance. This preliminary assessment allows optimization decisions to be made during fabrication rather than after completing multiple full devices, significantly reducing the time and material required to obtain reliable performance data.
2Manufacturing precision
If multiple devices are fabricated to compare different processing conditions, then performance optimization is achieved, but manufacturing cost increases
Solution Approach 1:
By measuring semiconductor properties during fabrication and using device models to predict final performance, the patent enables optimization decisions to be made with a single或少量 devices rather than requiring multiple complete devices. This reduces material consumption and fabrication costs while maintaining the ability to compare different processing conditions and achieve performance optimization.
3Reliability
If the top-down optimization process is used, then device performance is improved, but the process becomes inefficient
Solution Approach 1:
The patent reverses the traditional top-down approach by measuring properties during fabrication and using predictive modeling to assess final performance. This allows optimization feedback to be obtained during the fabrication process itself, dramatically improving optimization efficiency while maintaining the ability to achieve high device performance through informed processing condition selection.
Data Source
AI summary
An example methodology implementing the disclosed techniques includes receiving a plurality of measured semiconductor properties of one or more partially completed semiconductor devices, determining a measure of short circuit current density (JSC) of each of the one or more partially completed semiconductor devices, the JSC, measure based on a measure of semiconductor diffusion length (LD) and a measure of thickness, and determining a current voltage relationship of each of the one or more partially completed semiconductor devices. The method also includes calculating a current voltage (JV) curve based on the JSC, measure and the current voltage relationship of each of the one or more partially completed semiconductor devices, wherein the JV curve provides an indication of maximum achievable power point (Pmax) and open circuit voltage (Voc) of a semiconductor device completed from the one or more partially completed semiconductor devices, and determining a predicted performance characteristic of the semiconductor device.