Semiconductor Device Planarization via Peripheral Capping Layer
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to defects in land formation due to step differences between cell and peripheral regions, affecting the reliability of subsequent processes such as conductive pad and wiring layer formation.
Innovation Solution
A semiconductor device design where the bit line structure and peripheral capping layer are formed at the same level, eliminating step differences and ensuring a planar surface for the upper end of the bit line structure, which is covered by a conductive barrier and contact material layer, facilitating the formation of a continuously integrated conductive pad and wiring layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pattern miniaturization is implemented to increase integration, then device integration is improved, but step difference between cell region and peripheral region increases causing defects in land formation
Solution Approach 1:
The patent applies equipotentiality by forming the peripheral capping layer to have substantially the same upper surface level as the bit line structure, creating an equipotential surface that eliminates step differences between cell and peripheral regions. This resolves the manufacturing precision issue caused by miniaturization while maintaining high device integration.
2Manufacturing precision
If step difference between cell region and peripheral region is reduced to prevent defects, then land formation precision is improved, but device complexity increases due to additional capping layer formation
Solution Approach 1:
The peripheral capping layer serves multiple functions: it acts as a planarization layer to eliminate step differences, provides a base for subsequent conductive pad and wiring layer formation, and maintains structural integrity. This multi-functionality reduces the need for additional separate layers, thereby limiting the increase in device complexity while achieving improved manufacturing precision.
3Reliability
If planar surface is formed for bit line structure upper end, then subsequent process reliability is improved, but process complexity increases due to level matching requirements
Solution Approach 1:
The peripheral capping layer is formed in advance to establish the target upper surface level before subsequent land formation processes. This preliminary action creates a pre-defined planar reference surface, simplifying later process steps and reducing the complexity of level matching operations while ensuring high reliability of subsequent processes.
Data Source
AI summary
A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.