Semiconductor Peripheral Circuit Vertical Stacking
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Solution Overview
Problem
The reduction of semiconductor chip die area is limited by certain circuit types, particularly the peripheral circuit, which has a two-dimensional structure, making it difficult to minimize the chip area effectively due to its planar layout, whereas memory cell arrays can be stacked, but the peripheral circuit's area is harder to reduce in a similar manner.
Innovation Solution
The peripheral circuit is divided between the upper and lower surfaces of the substrates, allowing a two-dimensional structure on both planes, with high breakdown voltage transistors on the upper surface and low breakdown voltage transistors on the lower surface, enabling a more efficient use of space and reducing the overall chip area by optimizing the layout and placement of transistors and wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the peripheral circuit is arranged in a two-dimensional planar layout on a single substrate surface, then the circuit structure is simple and easy to manufacture, but the chip die area cannot be reduced effectively
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-dimensional planar layout to a three-dimensional stacked configuration. The peripheral circuit is divided into multiple layers stacked vertically on the substrate, with different functional blocks (memory cell arrays, peripheral circuits, pads) arranged at different heights. This vertical stacking enables significant reduction in the chip die area while maintaining manufacturability through standard semiconductor fabrication processes that can handle multi-layer structures.
Solution Approach 2:
The peripheral circuit is segmented into multiple functional blocks that are separately arranged in the vertical direction. Different circuit components (memory cell arrays, peripheral circuits, pads) are divided and placed at different substrate surfaces and intermediate layers, allowing each segment to be optimized independently while reducing the overall planar footprint of the chip.
2Quantity of substance
If memory cell arrays are stacked in three dimensions, then the storage capacity increases without increasing die area, but the peripheral circuit area remains difficult to reduce
Solution Approach 1:
The patent extends the vertical stacking approach to the peripheral circuit, not just the memory cell arrays. The peripheral circuit is divided and arranged at different substrate surfaces and intermediate layers in the vertical direction, enabling the peripheral circuit area to be reduced in the same manner as memory cell arrays, thereby resolving the contradiction between maintaining peripheral circuit functionality and reducing overall chip area.
Data Source
AI summary
A semiconductor device includes a first substrate and a plurality of electrode layers above the first substrate and separated from each other in a first direction. The device includes a plurality of plugs provided on upper surfaces or lower surfaces of the plurality of electrode layers and a plurality of columnar portions in the plurality of electrode layers and extending in the first direction. A charge storage layer is between a semiconductor layer of the columnar portions and the electrode layers. A second substrate is provided above the plurality of electrode layers. A plurality of first transistors is provided on an upper surface of the first substrate and are electrically connected to the plurality of plugs. A plurality of second transistors is provided on a lower surface of the second substrate and are electrically connected to the plurality of columnar portions.