Semiconductor Peripheral Dummy Structure and Spacer Contact
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Solution Overview
Problem
The manufacturing process of 3-dimensional nonvolatile memory devices is challenging due to significant step differences between cell and peripheral regions, leading to high defect probabilities and complexity.
Innovation Solution
A semiconductor device with a dummy structure and insulating spacers in the peripheral region, along with contact plugs that protrude from the spacers, is manufactured using a method involving alternating layers of materials with different etch selectivities, allowing for a more stable and integrated structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically in the cell region to increase integration density, then the degree of integration is improved, but a large step difference is created between the cell region and peripheral region
Solution Approach 1:
The patent divides the substrate into distinct cell region and peripheral region, with the cell region containing vertically stacked memory cells and the peripheral region containing planar circuits. This segmentation allows each region to be optimized independently - the cell region achieves high integration density through vertical stacking while the peripheral region maintains planar structure for circuit functionality, thereby resolving the step difference issue created by uniform vertical stacking across the entire substrate.
Solution Approach 2:
The patent transitions from 2-dimensional planar structure to 3-dimensional vertical stacking specifically in the cell region. By implementing vertical stacking only where needed for high-density memory storage and maintaining planar structure in the peripheral region for circuits, the patent achieves high integration density in the memory area while avoiding excessive step differences that would complicate manufacturing and increase defect rates.
2Quantity of substance
If 3-dimensional vertical stacking is implemented, then integration density is increased, but manufacturing complexity and defect probability increase
Solution Approach 1:
The patent applies vertical stacking technology locally only in the cell region where high integration density is required, while the peripheral region maintains traditional planar structure. This local application of 3-dimensional structure allows the patent to achieve high integration density in the memory storage area without subjecting the entire device to the manufacturing complexities and high defect probabilities associated with comprehensive vertical stacking, including issues with etch selectivity, spacer formation, and contact plug alignment across large step differences.
Data Source
AI summary
Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device may include a dummy structure formed on a peripheral region of a substrate, and insulating spacers configured to pass through the dummy structure and protrude from an upper surface of the dummy structure. The semiconductor device may include first contact plugs configured to pass through the insulating spacers and protrude from upper surfaces of the insulating spacers.