Semiconductor Device With Perpendicular Junction For Breakdown Voltage
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high drain-to-source breakdown voltage while maintaining low on-resistance, as increased impurity concentration in the π portion narrows the depletion layer extension, leading to breakdown issues and reduced breakdown voltage due to uneven channel region formation and ion implantation processes.
Innovation Solution
The semiconductor device features a semiconductor substrate with a drain region, channel regions, and an impurity region with perpendicular junction surfaces, where the gate electrode is partially separated, allowing for uniform depletion layer pinching and increased impurity concentration, thereby enhancing breakdown voltage and reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ion implantation and diffusion processes are used, then channel regions are formed, but uneven impurity distribution causes non-uniform depletion layer pinching and reduced breakdown voltage
Solution Approach 1:
The π portion is formed by ion implantation before the channel regions are formed. This preliminary action ensures that the high-impurity region is established first, providing a uniform foundation for subsequent channel region formation and ensuring uniform depletion layer pinching during breakdown
Solution Approach 2:
Conventional thermal diffusion processes are replaced with ion implantation technology. Ion implantation provides precise control over impurity concentration and distribution, eliminating the uneven impurity distribution caused by thermal diffusion and ensuring uniform depletion layer pinching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases the breakdown voltage to 600 V or higher while maintaining low on-resistance by ensuring uniform depletion layer pinching and controlled impurity concentration, preventing breakdowns at channel region corners and improving current path resistance.
Implementation Method 1
Ions of an n type impurity (for example, phosphor: P) are implanted into an entire surface of the n− type epitaxial layer
Implementation Method 2
ions of a p type impurity (for example, boron: B) are implanted, by using the gate electrode 33 as a mask
Implementation Method 3
by diffusing the n type impurity and the p type impurity through a thermal treatment, the n type impurity layer 40 and the channel regions 24 are formed
Data Source
AI summary
An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.