Semiconductor Integrated Circuit Phase Arithmetic for Ultrasonic Motor Timing
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Solution Overview
Problem
Existing semiconductor integrated circuits face increased computation load and memory storage requirements for precise timing adjustments of pulse output signals in ultrasonic motors, leading to inefficiencies in CPU processing and memory usage.
Innovation Solution
A semiconductor integrated circuit with a phase arithmetic circuit that includes digital multiplying, dividing, adding, and subtracting circuits to calculate new rise and fall setting count values, reducing the computational burden and memory needs by optimizing phase adjustments for pulse output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional pulse generation circuits with multiple delay circuits and latch circuits are used, then precise timing control is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent combines multiple delay circuits, latch circuits, AND circuits, OR circuits, and inverters into a single integrated pulse generation circuit. The counter unit, phase arithmetic unit, and pulse generation unit are merged into one cohesive system that generates multiple phase-shifted pulses simultaneously, reducing overall device complexity while maintaining timing precision.
Solution Approach 2:
The pulse generation circuit is designed to generate multiple pulse signals with different phases (60°, 120°, 180°, 240°, 300°, and 360°) using a single integrated system. The phase arithmetic unit can calculate various phase shifts, and the pulse generation unit can output multiple pulses with different duty cycles, making the circuit universally applicable for ultrasonic motor control.
2Measurement precision
If conventional pulse generation circuits with multiple latch circuits and logic circuits are used, then timing control is achieved, but power consumption increases
Solution Approach 1:
The patent merges multiple latch circuits and logic circuits into a single integrated pulse generation unit. By combining the functionality of six latch circuits, six AND circuits, one OR circuit, and multiple inverters into one unified system, the total power consumption is reduced while maintaining the ability to generate precisely timed pulse signals.
3Measurement precision
If phase adjustment is performed using conventional methods with multiple circuits, then timing accuracy is improved, but computation load on CPU increases
Solution Approach 1:
The phase arithmetic unit operates autonomously to calculate phase-shifted pulse timings without requiring CPU intervention. The unit automatically computes the timing for multiple phase shifts based on the input pulse signal, freeing the CPU from computation tasks and improving overall system productivity while maintaining high phase adjustment accuracy.
4Measurement precision
If conventional pulse generation with multiple logic circuits is used, then timing control is achieved, but the number of circuit components increases
Solution Approach 1:
The patent integrates multiple discrete logic circuits into a single pulse generation unit. Instead of using separate delay circuits, latch circuits, AND circuits, OR circuits, and inverters, the invention combines all these functions into one unified circuit that generates multiple phase-shifted pulses, thereby reducing the total number of circuit components.
Data Source
AI summary
An apparatus including an ultrasonic motor having an electrostrictive element of a stator for driving a rotor thereof; and a microcontroller having a central processing unit (CPU), a built-in memory (ROM) and a pulse generating circuit which generates an pulse output signal which is applied to the electrostrictive element of the ultrasonic motor, wherein the pulse generating circuit comprising a rise setting register, a fall setting register, a phase adjustment data register, a cycle data register, a phase arithmetic circuit, a counter, a 1st comparator, a 2nd comparator, and a pulse generator, wherein the counter starts to count up, incrementing its count value from a count initial value, wherein the cycle data register stores, as cycle data, a count maximum value for the counter to count up to it.