Semiconductor Pillar Alloy Formation for Structural Stability
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Solution Overview
Problem
The challenge in producing pillar-shaped semiconductor devices, such as Surrounding Gate MOS Transistors (SGTs), is the accurate formation of N+ and P+ regions, NiSi layers, and output wiring metal layers within the semiconductor pillar without causing bending or collapse, especially as the pillar size decreases to increase integration density.
Innovation Solution
A method involving the formation of a semiconductor pillar with impurity regions and alloy layers, where metal atoms react with semiconductor atoms during heat treatment to form alloy layers that protrude and contact the pillar's side surface, allowing for accurate impurity region formation and connection to wiring metal layers, while interlayer insulating layers separate from the pillar's side surface to manage stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pillar size is decreased to increase integration density, then the integration degree is improved, but the structural stability deteriorates causing bending or collapse
Solution Approach 1:
The patent applies local quality by forming alloy layers at specific locations within the semiconductor pillar structure. These alloy layers are positioned locally to provide mechanical support and prevent bending or collapse, while allowing the overall pillar dimensions to be reduced for higher integration density. The selective placement of material with different properties (alloy layer with higher mechanical strength) at critical locations resolves the contradiction between miniaturization and structural stability.
2Manufacturing precision
If alloy layers are formed within the semiconductor pillar, then the manufacturing precision of impurity regions is improved, but the process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming alloy layers in advance before subsequent processing steps. The alloy layers are created at predetermined positions and configurations, which then serve as templates or guides for subsequent impurity region formation. This preliminary structuring enables precise control over where impurity regions will form, improving manufacturing precision while managing process complexity through systematic sequencing.
Solution Approach 2:
The alloy layers function as intermediary structures that mediate between the manufacturing process and the final device structure. These intermediate alloy formations provide a controlled framework that guides subsequent processing steps, enabling precise impurity region formation. The intermediary alloy layers translate process parameters into precise structural outcomes, resolving the tension between precision requirements and process complexity.
3Stress or pressure
If interlayer insulating layers are separated from the pillar side surface, then the stress management is improved, but the structural integrity may be compromised
Solution Approach 1:
The patent applies segmentation by separating the interlayer insulating layers from the pillar side surface at specific regions. This segmentation creates distinct functional zones: areas where insulating layers contact the pillar for structural support, and areas where they are separated for stress management. By dividing the structure into these functional segments, the patent simultaneously achieves stress management benefits and maintains structural integrity through selective contact regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the precise formation of semiconductor regions serving as sources and drains within the pillar, reduces the occurrence of pillar bending, and ensures reliable connection to wiring metal layers, enhancing the integration density and performance of SGTs.
Implementation Method 1
the alloy layer contains metal atoms and semiconductor atoms, and the metal atoms react with the semiconductor atoms upon heat treatment to form the alloy layer
Implementation Method 2
the metal atoms react with the semiconductor atoms upon heat treatment to form the alloy layer
Implementation Method 3
during formation of the alloy layer, the donor or acceptor atoms are pushed out from the alloy layer
Data Source
AI summary
A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite layers, each including a metal layer and a semiconductor layer in contact with the metal layer, the semiconductor layer containing donor or acceptor atoms, and two interlayer insulating layers sandwiching the composite layers, such that a side surface of at least one of the two interlayer insulating layers is separated from a side surface of the semiconductor pillar. The laminated-structure surrounds the semiconductor pillar. A first heat treatment causes a reaction between the metal layer and the semiconductor layer to form an alloy layer, and brings the alloy layer into contact with the side surface of the semiconductor pillar. A second heat treatment to expands the alloy layer into the semiconductor pillar and diffuses dopant atoms into the semiconductor pillar to form an impurity region therein.