Semiconductor Pillar Structure for Low-Capacitance Bit Line Isolation

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Solution Overview

Problem

As semiconductor devices continue to shrink, increased capacitive coupling between adjacent components or interconnect structures leads to leakage current and short-circuit problems in memory devices.

Innovation Solution

The semiconductor structure is formed by disposing a first conductive pillar, an interface layer, a second conductive pillar, and an intermediate structure together as a dielectric plug, which reduces the risk of short circuits between the dielectric plug and the bit line structure, thereby improving electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the size of memory devices is reduced to increase storage density, then storage unit density is improved, but capacitive coupling between adjacent components increases leading to leakage current and short-circuit problems

Engineering Contradiction:
Improvestorage unit densityVSAvoidshort-circuit risk
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

An intermediate structure (dielectric layer) is introduced between the first conductive pillar and the bit line structure. This intermediate structure acts as a mediator that electrically isolates the conductive pillar from the bit line, preventing short circuits while allowing the device to maintain high storage density through miniaturization.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conductive plug is segmented into two separate conductive pillars (first and second conductive pillars) connected through an interface layer. This segmentation allows for better electrical isolation and reduced parasitic capacitance between adjacent components, thereby reducing leakage current and short-circuit risks while maintaining high density.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the contact area between conductive pillars is increased to reduce resistance, then electrical conductivity is improved, but device area increases leading to reduced storage density

Engineering Contradiction:
Improveelectrical conductivityVSAvoidstorage unit density
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The conductive pillars are extended in the vertical dimension rather than increasing horizontal contact area. The first conductive pillar extends from the active area up to the interface layer, and the second conductive pillar extends from the interface layer to the bit line structure, creating a three-dimensional conductive path that reduces resistance without consuming additional planar area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive plug is formed as a composite structure with multiple materials: the first conductive pillar material, the interface layer material, and the second conductive pillar material. This composite structure optimizes electrical conductivity through material selection while maintaining compact dimensions for high storage density.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS12347766B2Semiconductor structure and method for forming the same
Publication Date: 2025.07.01 WINBOND ELECTRONICS CORP
  • US12347766B2 patent drawing
  • US12347766B2 patent drawing
  • US12347766B2 patent drawing

AI summary

A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a bit line structure, a first conductive pillar, an interface layer, a second conductive pillar, and an intermediate structure. The substrate has an active area and an isolation structure. The bit line structure is disposed on the active area. The first conductive pillar is disposed on the active area. The interface layer is disposed on a top surface of the first conductive pillar. The second conductive pillar is disposed on the interface layer. The intermediate structure is disposed between the first conductive pillar and the bit line structure.