Semiconductor Pillar Fabrication via Etch Stop Segmentation
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Solution Overview
Problem
Conventional semiconductor devices with vertical channels face issues such as pillar patterns leaning or adhering due to small pillar neck diameters, uneven pillar heights, voids, and seams in conductive layers, leading to channel length variations and substrate damage during etching.
Innovation Solution
A method involving sequential formation of etch stop layers, conductive layers, and hard mask patterns on a substrate, followed by etching to create opened regions, forming pillar patterns, and depositing a gate insulation layer, which prevents pillar leaning and ensures even heights, and a gate electrode is formed by etching the conductive layer between pillar patterns using the gate hard mask layer as a barrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the pillar neck diameter is reduced to improve cell efficiency, then channel length is improved, but pillar patterns lean or adhere to each other
Solution Approach 1:
The invention introduces an etch stop layer that segments the pillar structure into distinct regions (pillar head, pillar neck, and pillar base). This segmentation allows the pillar neck to have a smaller diameter for improved channel length while the pillar base maintains sufficient width for stability, preventing leaning and adhesion between adjacent pillars.
Solution Approach 2:
The etch stop layer creates local quality variations in the pillar structure by providing a wider base region compared to the narrow neck region. This local expansion at the base provides mechanical support and stability, while the narrow neck maintains the desired channel length, resolving the contradiction between these two requirements.
2Device complexity
If etching is performed without an etch stop layer to simplify the process, then manufacturing complexity is reduced, but pillar heights become uneven
Solution Approach 1:
The etch stop layer is formed in advance before the pillar etching process. This preliminary action establishes a predetermined depth reference that ensures all pillars are etched to the same depth, guaranteeing uniform pillar heights and consistent channel lengths across the device structure.
3Ease of manufacture
If conductive layer is filled between adjacent pillar patterns to form gate electrode, then gate electrode formation is achieved, but voids and seams are formed due to high aspect ratio
Solution Approach 1:
The gate insulation layer is formed on the pillar sidewalls before filling the conductive layer. This preliminary insulation layer creation facilitates subsequent conductive layer formation by providing a proper interface, ensuring complete filling without voids or seams, and maintaining conductive layer integrity throughout the gate electrode formation process.
4Manufacturing precision
If etching is performed on conductive layer with voids and seams, then gate electrode patterning is achieved, but gate insulation layer and substrate are punched through
Solution Approach 1:
The gate insulation layer is formed on the pillar sidewalls before filling the conductive layer. This preliminary insulation layer creation facilitates subsequent conductive layer formation by providing a proper interface, ensuring complete filling without voids or seams, and maintaining conductive layer integrity throughout the gate electrode formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents pillar patterns from leaning, ensures even heights and channel lengths, avoids voids and seams in conductive layers, and enhances the reliability and stability of semiconductor devices, particularly for sizes below 40 nm, improving yield.
Implementation Method 1
forming a gate insulation layer on a sidewall of each of the opened regions
Implementation Method 2
forming a gate insulation layer on a sidewall of each of the opened regions
Implementation Method 3
forming a plurality of opened regions by etching the second etch stop layer, the conductive layer and the first etch stop layer
Implementation Method 4
forming on each pillar pattern a gate electrode from said portion of the conductive layer by etching portions of the conductive layer between the pillar patterns using the gate hard mask layer pattern as an etching barrier
Data Source
AI summary
In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a sidewall of each of the opened regions. A pillar pattern is formed in each opened region. On each pillar pattern, a gate electrode, which encloses the pillar pattern, is formed by removing the conductive layer between the pillar patterns.