Semiconductor Pillar Fabrication via Intersecting Line-and-Space Masks
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Solution Overview
Problem
Current semiconductor device fabrication methods struggle with miniaturization of three-dimensional devices due to reliance on time-consuming extreme ultraviolet photolithography technologies, necessitating an alternative approach to achieve smaller dimensions without waiting for advancements in photolithography.
Innovation Solution
A semiconductor device fabrication method involving a series of layer stacking, masking, and etching processes to create miniaturized three-dimensional structures, where layers are patterned and etched to form pillars with dimensions smaller than those achievable by conventional photolithography, using materials like silicon nitride, amorphous silicon, and photoresist layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If extreme ultraviolet photolithography technology is used to achieve miniaturization, then smaller dimensions can be realized, but the exposure time becomes excessively long
Solution Approach 1:
The fabrication process is divided into multiple sequential steps: forming first and second patterns in different directions, creating side wall layers, and iteratively refining the structure. This segmentation allows each step to work within conventional photolithography capabilities while achieving sub-critical dimensions through cumulative refinement rather than requiring a single high-precision exposure step
Solution Approach 2:
The invention transitions from two-dimensional planar patterning to three-dimensional vertical structures by forming side wall layers and stacked patterns. This dimensional transition enables further miniaturization in the vertical dimension while maintaining compatibility with conventional photolithography in the horizontal dimension, avoiding the time penalty of EUV exposure
2Productivity
If conventional photolithography technology is used, then the fabrication process is simpler and faster, but the achievable dimension is larger than desired
Solution Approach 1:
The method performs preliminary patterning actions to create sacrificial structures and side wall layers that define subsequent pattern dimensions. These preliminary structures are formed using conventional photolithography, establishing a foundation that enables further miniaturization in later steps without requiring advanced lithography
Solution Approach 2:
Side wall layers and sacrificial structures serve as intermediary elements that mediate between the capabilities of conventional photolithography and the requirements for sub-critical dimensions. These intermediaries are formed by standard processes and then used to define final pattern dimensions through self-aligned etching, bridging the gap between available lithography and desired precision
Data Source
AI summary
According to a disclosed semiconductor device fabrication method according to one embodiment of the present invention, a layer having a line-and-space pattern extending in one direction is etched using another layer having a line-and-space pattern extending in another direction intersecting the one direction, thereby obtaining a mask having two-dimensionally arranged dots. An underlying layer is etched using the mask, thereby providing two-dimensionally arranged pillars.