Semiconductor Interconnects Using Flat and Pillar Contacts
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Solution Overview
Problem
Conventional methods for forming interconnects between semiconductor devices require precise alignment and are prone to substrate damage due to thermal expansion mismatches, leading to high failure rates and potential device failure.
Innovation Solution
The method involves depositing flat contacts on one semiconductor device and forming pillar-like plated contacts on another, allowing for alignment and joining to create robust electrical interconnects that absorb thermal expansion stresses, with an adhesive material for mechanical stabilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metallic contacts are used with elevated temperature melting and cold welding, then electrical interconnects are formed between semiconductor devices, but the devices require very precise alignment and are prone to substrate damage due to thermal expansion mismatches
Solution Approach 1:
The invention changes the formation parameters of contacts by using deposition for flat contacts and plating for pillar-like contacts, creating complementary geometries that reduce alignment sensitivity. This parameter change in contact formation methodology resolves the contradiction by maintaining reliability while reducing manufacturing precision requirements
Solution Approach 2:
The invention creates a composite interconnect structure combining deposited flat contacts with plated pillar-like contacts. This composite approach leverages the advantages of both deposition (flat surface area) and plating (pillar structure) to achieve reliable electrical connection with relaxed alignment tolerances
2Reliability
If elevated temperatures are used to melt contacts into each other, then electrical conduction is achieved, but thermal expansion mismatches between dissimilar substrate materials cause stresses that lead to substrate damage and device failure
Solution Approach 1:
The invention performs preliminary alignment and contact formation at lower temperatures before final joining, creating the flat contact and pillar-like contact structures in advance. This preliminary action allows the contacts to be pre-formed with optimal geometries that compensate for thermal expansion differences, reducing stress during subsequent thermal cycles
Solution Approach 2:
The flat contact and pillar-like contact structures serve as intermediaries between dissimilar substrate materials. These contact structures absorb and distribute thermal expansion stresses, acting as a buffer that protects the substrates from damage while maintaining electrical conduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces alignment tolerances and contact failure rates, enabling denser and more reliable interconnect arrays with improved thermal stress management.
Implementation Method 1
stresses introduced into the mating contacts as the device cools can also lead to substrate damage and device failure
Implementation Method 2
joining the plurality of first contacts to the plurality of plated contacts to form the interconnects
Data Source
AI summary
Systems and methods are disclosed for forming interconnects between semiconductor devices in accordance with one or more embodiments of the present invention. For example, a method of forming interconnects between semiconductor devices includes depositing a plurality of first contacts on a plurality of corresponding first pads of a first semiconductor device; forming a plurality of plated contacts on a plurality of corresponding second pads of a second semiconductor device; aligning the plurality of first contacts with the plurality of plated contacts; and joining the plurality of first contacts to the plurality of plated contacts to form the interconnects between the first semiconductor device and the second semiconductor device.