Self-aligned Gate Electrode Formation for Semiconductor Pillars
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Solution Overview
Problem
The existing methods for forming gate electrodes around pillar-shaped silicon layers in SGTs face challenges such as small process margins, disconnection or open of gate lines, and inability to achieve self-alignment, leading to variations in gate length and increased occupancy areas, which hinder high-yield production of integrated circuits.
Innovation Solution
A method involving the formation of a protective silicon nitride film-based sidewall, followed by lithography to create a resist pattern, and subsequent etching to form a gate electrode and gate line, ensuring self-alignment and desired film thickness, while using CMP to control gate length and minimize variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithography and etching methods are used to form gate electrodes around pillar-shaped silicon layers, then gate electrodes can be formed, but process margins are small and gate lines may disconnect or open
Solution Approach 1:
A protective film is formed on the pillar-shaped silicon layer before the gate electrode formation process. This preliminary protective layer prevents etching damage to the silicon layer during subsequent gate line etching, eliminating the risk of gate line disconnection and ensuring reliable gate electrode formation with adequate process margins
2Manufacturing precision
If conventional self-alignment methods are used, then some alignment is achieved, but precise self-alignment cannot be obtained leading to gate length variations
Solution Approach 1:
The protective film serves a dual function: it protects the pillar-shaped silicon layer during etching and simultaneously acts as a self-aligned mask that defines the gate electrode position. The gate line is etched to expose the protective film, which then automatically defines the precise boundary between the gate electrode and the silicon layer, achieving accurate self-alignment without complex additional alignment steps
3Area of stationary object
If conventional gate electrode formation methods are used, then gate electrodes can be formed, but occupancy areas increase
Solution Approach 1:
The protective film is formed preliminarily on the pillar-shaped silicon layer before gate electrode formation. This allows the gate electrode to be precisely positioned and sized, minimizing the occupancy area while ensuring complete coverage of the silicon layer sidewall, thereby achieving high integration density without compromising fabrication capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of gate electrodes in a self-alignment manner with precise film thickness, reducing the risk of gate line disconnection and variations, thereby improving the process margin and reducing circuit area.
Implementation Method 1
etching back the protective film to form a protective film-based sidewall
Implementation Method 2
using CMP to control gate length and minimize variations
Data Source
AI summary
It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.