Semiconductor Pillar Design Reducing Selection Gate Complexity
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Solution Overview
Problem
Existing semiconductor memory devices with increased vertical integration face challenges due to the high number of selection gates and associated circuits, which complicate production and reduce efficiency, especially as silicon pillar widths decrease, making it difficult to achieve low impurity concentrations and proper gate work functions.
Innovation Solution
The semiconductor device design reduces the number of selection gates per pillar-shaped semiconductor layer by arranging pillar-shaped layers with only control gates in a line and connecting them with internal lines, allowing for fewer selection gates and simplified production steps, while using metal contact electrodes with specific work functions to achieve desired semiconductor properties without forming diffusion layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of selection gates is increased to control more memory cells vertically, then the memory integration density is improved, but the device complexity and number of production steps increase
Solution Approach 1:
The memory array is divided into multiple banks, with each bank having its own independent selection gate. This segmentation allows multiple memory cells to be controlled with fewer selection gates overall, as each bank can be independently accessed without requiring selection gates for every individual cell column.
Solution Approach 2:
Each selection gate serves multiple functions by controlling access to multiple memory cell columns across different word lines. A single selection gate can select columns for multiple different word lines, allowing one gate to replace what would traditionally require multiple gates in a non-banked architecture.
2Quantity of substance
If the silicon pillar width is decreased to increase integration density, then the memory capacity is improved, but the difficulty of forming proper impurity concentrations and work functions increases
Solution Approach 1:
The patent changes the material parameter (work function) of the gate electrode from conventional materials to metal materials with specifically selected work functions (4.0-4.2 eV for n-type, 5.0-5.2 eV for p-type). This parameter change allows proper threshold voltage control in ultra-narrow pillars without requiring precise impurity concentration control, which becomes difficult at small dimensions.
3Reliability
If metal contact electrodes with specific work functions are used, then the threshold voltage control is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent specifies precise work function parameter ranges for metal materials (4.0-4.2 eV for n-type channels, 5.0-5.2 eV for p-type channels). By controlling this single material parameter, the patent achieves reliable threshold voltage control without requiring complex multi-step manufacturing processes, simplifying production compared to methods requiring precise impurity diffusion control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the number of selection gates and production steps, enhances semiconductor layer functionality, and allows for efficient semiconductor device operation by decreasing the complexity of gate formation and increasing the integration density.
Implementation Method 1
metal contact electrodes with specific work functions to achieve desired semiconductor properties without forming diffusion layers
Data Source
AI summary
A semiconductor device includes a first pillar-shaped semiconductor layer, a first selection gate insulating film, a first selection gate, a first gate insulating film, a first contact electrode, a first bit line connected to an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the first contact electrode, a second pillar-shaped semiconductor layer, a layer including a first charge storage layer, a first control gate, a layer including a second charge storage layer and formed above the first control gate, a second control gate, a second gate insulating film, a second contact electrode having an upper portion connected to an upper portion of the second pillar-shaped semiconductor layer, and a first lower internal line that connects a lower portion of the first pillar-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer.