Semiconductor Pillar Segmentation for Low Resistance
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing ON-state resistance while maintaining high withstand voltage and saturated drain current density, particularly due to limitations in impurity concentration variations and pillar region widths, which affect switching noises and current conduction.
Innovation Solution
The semiconductor device incorporates a p− type pillar region electrically connected to the gate electrode and an n− type pillar region with a specific impurity concentration, along with a unique insulating portion structure, to form accumulation and inversion channels, reducing ON-state resistance and switching noises while maintaining high withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity concentration in pillar regions is increased to reduce ON-state resistance, then ON-state resistance decreases, but withstand voltage decreases
Solution Approach 1:
The semiconductor device divides the pillar regions into two distinct types: first pillar regions with higher impurity concentration (1×10^16 to 1×10^18 atoms/cm³) and second pillar regions with lower impurity concentration (1×10^15 to 1×10^17 atoms/cm³). This segmentation allows each region to serve different functions - the first pillar regions provide low resistance conduction paths while the second pillar regions maintain high breakdown voltage, thereby resolving the contradiction between reducing ON-state resistance and maintaining withstand voltage.
Solution Approach 2:
Different impurity concentrations are applied to different spatial locations within the device. The first pillar regions positioned near the source/drain contacts have higher impurity concentration to reduce contact resistance, while the second pillar regions positioned elsewhere have lower impurity concentration to maintain high withstand voltage. This local differentiation of material properties optimizes both contradictory requirements simultaneously.
2Productivity
If pillar region width is reduced to increase density, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The device structure segments the pillar regions into two groups with different widths and impurity concentrations. The first pillar regions have width of 0.5-2.0 μm with higher impurity concentration, while the second pillar regions have width of 0.3-1.5 μm with lower impurity concentration. This segmentation provides design flexibility that relaxes manufacturing precision requirements, as the less critical second pillar regions can tolerate wider dimensional variations while the critical first pillar regions maintain optimized dimensions.
Solution Approach 2:
The invention changes multiple parameters simultaneously - both the width and impurity concentration of pillar regions are varied across different regions. By coupling these parameter changes, the device achieves high density through reduced widths while compensating for manufacturing variations through adjusted impurity concentrations, thereby reducing the stringency of precision requirements.
3Reliability
If impurity concentration is uniformly increased throughout the device, then ON-state resistance decreases, but switching noises increase
Solution Approach 1:
The device segments the impurity distribution into two distinct zones: first pillar regions with higher impurity concentration that provide low resistance paths, and second pillar regions with lower impurity concentration that minimize switching noises. This spatial segmentation of impurity concentrations allows the device to achieve low ON-state resistance without the penalty of increased switching noises that would result from uniform high impurity concentration throughout the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces ON-state resistance and switching noises while preserving high withstand voltage and saturated drain current density, enhancing the semiconductor device's performance and stability.
Implementation Method 1
form accumulation and inversion channels
Implementation Method 2
form accumulation and inversion channels
Data Source
AI summary
A semiconductor device comprising:a first electrode; a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; a fifth semiconductor region;an insulating portion that is provided between the second semiconductor region and the fifth semiconductor region and between the third semiconductor region and the fifth semiconductor region;a sixth semiconductor region; a seventh semiconductor region;a gate electrode;a gate insulating layer;a second electrode; anda third electrode that is provided on the third semiconductor region and electrically connected to the third semiconductor region and the gate electrode.