Semiconductor Pillar Layout for Self-Aligned Bit and Word Lines

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Solution Overview

Problem

The existing semiconductor structure formation processes, such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP), are complex and costly, and the use of new photomasks affects overlay accuracy.

Innovation Solution

A method involving bit line and word line isolation trenches forming semiconductor pillars, with a bit line metal layer surrounding the sidewall of the semiconductor pillar, using sacrificial layers with different etching selectivities to simplify the process and eliminate the need for new photomasks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) process is used to form word line structure, then the semiconductor structure can be formed with precise alignment, but the process complexity and cost increase significantly

Engineering Contradiction:
Improveoverlay accuracyVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The method performs preliminary patterning of bit line isolation trenches and word line isolation trenches before forming the semiconductor pillars. By pre-defining the isolation structures with different orientations (first direction for bit line, second direction for word line), the subsequent pillar formation automatically achieves precise alignment without requiring complex SADP or SAQP processes. This preliminary action eliminates the need for multiple photomask steps while maintaining manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation structures serve as intermediary elements that mediate between the photomask patterning and the final semiconductor pillar formation. By using the isolation trenches as reference structures, the method enables automatic self-alignment of the semiconductor pillars without requiring additional alignment steps. The isolation structures act as a bridge that transfers the patterning information from the photomask to the final device structure with high precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) process is used to form word line structure, then the semiconductor structure can be formed with precise alignment, but the manufacturing cost increases

Engineering Contradiction:
Improveoverlay accuracyVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The method performs preliminary patterning of bit line isolation trenches and word line isolation trenches before forming the semiconductor pillars. By pre-defining the isolation structures with different orientations (first direction for bit line, second direction for word line), the subsequent pillar formation automatically achieves precise alignment without requiring complex SADP or SAQP processes. This preliminary action eliminates the need for multiple photomask steps while maintaining manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation structures serve as intermediary elements that mediate between the photomask patterning and the final semiconductor pillar formation. By using the isolation trenches as reference structures, the method enables automatic self-alignment of the semiconductor pillars without requiring additional alignment steps. The isolation structures act as a bridge that transfers the patterning information from the photomask to the final device structure with high precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If new photomask is used to form self-aligned word line metal layer and word line isolation layer, then the word line structure can be formed, but the overlay accuracy is affected

Engineering Contradiction:
Improveprocess feasibilityVSAvoidoverlay accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The isolation structures serve multiple functions: they define the bit line regions, define the word line regions, and provide self-alignment references for subsequent processing steps. By making the isolation structures multi-functional, the method eliminates the need for separate photomasks for bit line and word line patterning, thereby maintaining overlay accuracy while ensuring process feasibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The isolation structures automatically provide alignment references for the formation of semiconductor pillars and subsequent metal layers. The self-aligned nature of the process allows the previously formed isolation structures to serve as their own alignment references, eliminating the need for additional photomask alignment steps that would degrade overlay accuracy.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method simplifies the process, reduces costs, and enhances control over channels and carrier mobility while improving the semiconductor structure's performance by eliminating the need for new photomasks and addressing overlay accuracy issues.

Implementation Method 1

performing a patterned etching on the base to form a plurality of word line isolation trenches extending along a second direction

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

using sacrificial layers with different etching selectivities

Methodology Applied
Scientific EffectEtching selectivity:

Data Source

PatentUS12382627B2Semiconductor structure and forming method thereof
Publication Date: 2025.08.05 CHANGXIN MEMORY TECH INC
  • US12382627B2 patent drawing
  • US12382627B2 patent drawing
  • US12382627B2 patent drawing

AI summary

The present disclosure discloses a semiconductor structure and a forming method thereof. The forming method includes: providing a base, where the base is provided with a plurality of bit line isolation trenches extending along a first direction and an isolation structure located in the bit line isolation trench; performing a patterned etching on the base to form a plurality of word line isolation trenches extending along a second direction, where the plurality of bit line isolation trenches and the plurality of word line isolation trenches form a plurality of semiconductor pillars in the base; forming a bit line metal layer on a surface of the semiconductor pillar under the word line isolation trenches, where the bit line metal layer surrounds a sidewall of the semiconductor pillar.