Semiconductor Pillar Layout With Air Gaps for Bit Line Capacitance
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Solution Overview
Problem
The integration of dynamic memory structures faces challenges in reducing the size of functional devices while maintaining optimal electrical properties due to increased coupling capacitance between adjacent bit lines, which is exacerbated by the reduced spacing between bit lines in vertical gate-all-around transistor configurations.
Innovation Solution
A manufacturing method that involves forming third trenches between adjacent bit lines to create gaps in the second isolation layer, utilizing the lower dielectric constant of air to reduce parasitic capacitance, and incorporating self-aligned quadruple patterning to form semiconductor pillars and bit lines with precise alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the spacing between adjacent bit lines is reduced to increase integration density, then the area occupied by each transistor is reduced, but the coupling capacitance between adjacent bit lines increases and deteriorates electrical properties
Solution Approach 1:
The patent introduces a low-k dielectric material as an intermediary substance between adjacent bit lines. This intermediary layer has a dielectric constant lower than the surrounding isolation layer, thereby reducing the coupling capacitance between bit lines while maintaining the reduced spacing configuration for higher integration density.
Solution Approach 2:
The patent applies different dielectric properties to different regions: the bulk isolation layer maintains its original high-k properties for good isolation, while specific regions between adjacent bit lines are filled with low-k dielectric material to locally reduce coupling capacitance. This localized quality adjustment addresses the capacitance issue without compromising overall structure.
2Productivity
If the size of functional devices is reduced to increase integration density, then more devices can be packed into the same area, but the electrical properties of small-size devices deteriorate
Solution Approach 1:
The low-k dielectric material serves as a mediator that reduces parasitic coupling effects on small-size devices. By lowering the dielectric constant in critical regions, the patent minimizes capacitive interference that would otherwise disproportionately affect smaller devices, thereby maintaining their electrical properties despite size reduction.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) in specific regions to optimize electrical properties. By selecting materials with lower dielectric constants for regions between bit lines, the patent reduces parasitic capacitance values that would otherwise limit the performance of scaled-down devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the electrical properties of semiconductor structures by reducing parasitic capacitance and improving integration density, while avoiding issues related to doping control and short-channel effects in junctionless transistors.
Implementation Method 1
a part of the second isolation layer in the third trenches has gaps
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which relate to the field of semiconductors. The method includes: providing a base; forming a plurality of first trenches extending along a first direction in the base, the first trenches forming the base into semiconductor layers arranged at intervals, and filling the first trenches with a first isolation layer; forming a plurality of second trenches extending along a second direction in the semiconductor layers and the first isolation layer, to form the semiconductor layers into a plurality of separate semiconductor pillars and initial bit lines located below the semiconductor pillars; forming third trenches parallel to the first trenches at positions lower than the second trenches; and filling the second trenches and the third trenches with a second isolation layer, where a part of the second isolation layer in the third trenches has gaps.