Press-Pack Semiconductor Pillar Structure for Uniform Chip Pressure
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Solution Overview
Problem
Existing power semiconductor devices face challenges with non-uniform pressure and temperature distribution across chips due to micron-level thickness variations, surface flatness issues, and thermal warpage, leading to premature failures and performance limitations.
Innovation Solution
A semiconductor device design featuring tall pillars and a thermal coupler that thermally couples these pillars to improve mechanical compliance and uniform pressure distribution, while maintaining thermal cross-coupling between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional press-pack power semiconductor devices use flat electrodes and rigid mounting, then manufacturing is simple, but pressure distribution across chips becomes non-uniform due to micron-level thickness variations and surface flatness issues
Solution Approach 1:
The patent changes the geometric parameters of the electrode structure by introducing tall pillars (with height significantly greater than chip thickness) instead of flat electrodes. This parameter change allows the pillars to deform elastically under compression, adapting to micron-level thickness variations and surface flatness issues, thereby achieving uniform pressure distribution across all chips while maintaining manufacturing simplicity.
Solution Approach 2:
The tall pillar structure acts as a pre-designed compliance mechanism that compensates for manufacturing tolerances before the device operates. The pillars are designed with sufficient height and elastic properties to absorb thickness variations and surface irregularities, providing 'cushioning' against pressure non-uniformity before it can affect chip performance or reliability.
2Manufacturing precision
If tall pillars are used to improve pressure uniformity, then pressure distribution becomes more uniform, but thermal coupling between chips deteriorates due to increased thermal resistance
Solution Approach 1:
The patent introduces a thermal coupler as an intermediary component that bridges the tall pillars and provides a low-thermal-resistance path for heat transfer. The thermal coupler is in thermal contact with multiple pillars, allowing heat to conduct laterally between them, thereby compensating for the increased thermal resistance of the tall pillars and maintaining effective thermal coupling between chips.
Solution Approach 2:
The thermal coupler introduces a lateral heat conduction dimension by connecting multiple tall pillars through a thermally conductive structure. This creates an additional heat transfer pathway that bypasses the high thermal resistance of the pillar lengths, effectively coupling chips thermally through the pillar array without requiring the pillars themselves to be short.
3Stability of the object's composition
If rigid electrode mounting is used, then structural stability is high, but thermal warpage causes pressure imbalance and premature failures
Solution Approach 1:
The patent changes the mechanical compliance parameter of the electrode structure by using tall pillars with sufficient height-to-diameter ratios. This allows the structure to remain stable overall while providing local compliance at the chip contact points, enabling the electrodes to accommodate thermal warpage without losing structural integrity or causing pressure imbalance.
Solution Approach 2:
The tall pillar structure transitions from a rigid, static mounting system to a more dynamic system that can elastically deform in response to thermal expansion and warpage. This dynamic compliance allows the structure to adapt to thermal stresses during operation, preventing pressure imbalance and improving device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved uniformity in pressure and temperature distribution across semiconductor units, enhancing the reliability and performance of the device by reducing mechanical and thermal decoupling effects.
Implementation Method 1
a thermal coupler arranged within the housing between the plurality of semiconductor units and the electrode plate of the first housing electrode; wherein the thermal coupler is configured to extend between at least some of the first array of pillars so as to thermally couple the at least some of the first array of pillars to one another
Implementation Method 2
tall pillars and a thermal coupler that thermally couples these pillars to improve mechanical compliance and uniform pressure distribution
Data Source
AI summary
A semiconductor device is provided and includes a housing having first and second opposing housing electrodes and semiconductor units within the housing and coupled to the housing electrodes by pressure. The first housing electrode includes an electrode plate. A thermal coupler is provided between the semiconductor units and the electrode plate. A first array of pillars extend between the semiconductor units and the thermal coupler. A second array of pillars extend between the thermal coupler and the electrode plate. The semiconductor units are electrically coupled to the electrode plate via the first and second arrays of pillars. The thermal coupler extends between at least some of the first array of pillars so as to thermally couple the at least some of the first array of pillars to one another.