Semiconductor Interconnect Layout for Dense Pin Access Routing
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Solution Overview
Problem
The design of integrated circuits (ICs) faces challenges in achieving smaller chip areas and better performance due to complex process rules and limited routing resources, particularly in advanced processes, necessitating a novel approach for effective pin access.
Innovation Solution
An optimized layout and metal structure are implemented, featuring Fin Field-Effect Transistors (FinFETs) and Gate All Around (GAA) transistors with a multilayer interconnection (MLI) structure, including multiple metal layers with varying thicknesses and pitches, to enhance routing efficiency and chip packing density while reducing intra-cell coupling capacitance and power line resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional routing methods are used in advanced processes, then routing resources are sufficient for basic connections, but chip area increases and performance deteriorates due to lack of routing resources
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical routing by stacking multiple metal layers (M1-M6) with varying pitches. Different metal layers serve different routing functions: M1-M3 for fine-pitch local connections, M4-M6 for coarse-pitch long-distance connections. This dimensional change enables simultaneous achievement of small chip area and sufficient routing resources through vertical interlayer via connections.
2Productivity
If metal layer pitch is reduced to increase routing density, then routing efficiency improves, but intra-cell coupling capacitance increases
Solution Approach 1:
The patent applies different pitch values to different metal layers based on local routing requirements. M1-M3 layers use first pitch values optimized for fine-grain local connections within cells, while M4-M6 layers use second pitch values optimized for coarse-grain long-distance inter-cell connections. This local quality differentiation reduces unnecessary capacitance while maintaining routing efficiency.
3Adaptability or versatility
If power line width is reduced to increase routing resources, then routing density improves, but power line resistance increases
Solution Approach 1:
The patent distributes power delivery across multiple metal layers (M4-M6) with varying pitches. Thicker power lines are implemented in upper layers (M4-M6) where wider pitch allows for lower resistance, while finer pitch layers (M1-M3) handle signal routing. This vertical distribution reduces overall power line resistance while maintaining sufficient routing resources.
4Manufacturing precision
If complex process rules are followed to ensure manufacturing precision, then device performance is reliable, but design flexibility and routing resources are limited
Solution Approach 1:
The patent segments the interconnection system into multiple independent metal layers (M1-M6) with different pitch specifications. Each layer can be independently designed and optimized according to specific routing requirements while adhering to process rules. This segmentation provides design flexibility through selective pitch assignment: finer pitches for signal routing, coarser pitches for power delivery, all while maintaining process compliance.
Data Source
AI summary
A semiconductor device includes a substrate having a first active region disposed in a first region of a substrate and a second active region disposed in a second region of the substrate. A first gate stack is disposed over the first active region and a second gate stack is disposed over the second active region, the first and second gate stacks having elongated shapes oriented in a first direction. A first metal layer is disposed over the first gate stack and the second gate stack. The first metal layer includes first metal layer structures oriented in a second direction orthogonal to the first direction. A second metal layer disposed over the first metal layer. The second metal layer includes second metal layer structures oriented in the first direction. A third metal layer is disposed over the second metal layer. The third metal layer includes a third metal layer structures oriented in the second direction.