Semiconductor Device Pin Diode Insulating Region Carrier Flow

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Solution Overview

Problem

Existing semiconductor devices, such as free-wheeling diodes, face challenges in widening the safe operation region while shortening recovery time, which is crucial for power conversion devices like inverters, due to issues with current and voltage oscillations during recovery.

Innovation Solution

A semiconductor device design featuring a p-intrinsic-n (pin) diode structure with specific semiconductor regions and an insulating region configuration that includes a p-type high-concentration layer, channel region, and insulating regions to manage carrier flow and reduce hole injection, thereby enhancing recovery speed and breakdown tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional diode structure is used, then manufacturing is simple, but recovery time is long and safe operation region is narrow

Engineering Contradiction:
Improvesafe operation regionVSAvoiddiode structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The diode structure is segmented into multiple functional regions: a first semiconductor region, a second semiconductor region, a third semiconductor region, and an insulating region. This segmentation allows each region to perform specific functions that collectively improve recovery characteristics and safe operation region while managing device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the diode are assigned different doping concentrations and material properties to optimize local performance. The high-concentration layer in the insulating region and the specific conductivity types in different semiconductor regions create local quality variations that enhance overall device performance.

Inventive Principle:
Principle #3Local quality

2Loss of time

If recovery time is shortened, then productivity improves, but voltage oscillation and avalanche effects increase

Engineering Contradiction:
Improverecovery timeVSAvoidvoltage oscillation and avalanche effects
Core Design Contradiction:
Loss of timeVSObject-affected harmful factors

Solution Approach 1:

The insulating region acts as an intermediary element between the semiconductor regions, controlling carrier flow and reducing direct interaction that causes avalanche effects. The channel region formed in the insulating region mediates carrier transport, enabling faster recovery while suppressing harmful oscillations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The device utilizes parameter changes in carrier concentration and conductivity type across different regions to control recovery characteristics. The high-concentration layer and varying doping levels enable parameter optimization that reduces recovery time while maintaining stability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If hole injection is reduced, then breakdown tolerance improves, but carrier flow management becomes more complex

Engineering Contradiction:
Improvebreakdown toleranceVSAvoidcarrier flow management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating region extracts or removes the harmful hole injection effect by providing a barrier that prevents excessive hole flow into critical regions. This extraction of harmful carriers improves breakdown tolerance while the structured design manages the complexity of carrier flow.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively speeds up recovery and improves breakdown tolerance, enlarging the safe operation area by reducing reverse current and suppressing avalanche effects, leading to improved performance in power conversion devices.

Implementation Method 1

an insulating region configured to include a p-type high-concentration layer, a channel region, and a plurality of insulating regions

Methodology Applied
Scientific EffectElectrical field: Electric Field

Implementation Method 2

suppressing avalanche effects, leading to improved performance in power conversion devices

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS10141455B2Semiconductor device
Publication Date: 2018.11.27 KK TOSHIBA
  • US10141455B2 patent drawing
  • US10141455B2 patent drawing
  • US10141455B2 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.