Semiconductor Pin Pattern Concentration for Routing Flexibility
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Solution Overview
Problem
Current design rule sets for semiconductor devices face challenges in optimizing pin pattern placement and routing, leading to inefficiencies in wiring patterns and access points, particularly in avoiding the 'stacked 2AP pattern' circumstance which restricts via-based connections.
Innovation Solution
The method involves generating a layout diagram where a majority of pin patterns are concentrated in the M*1st level, with specific arrangements along tracks to minimize the number of wiring patterns in the M*2nd level and maximize access points, thereby improving routability and flexibility by aligning pin patterns along fewer tracks and ensuring sufficient overlap for via-based connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pin patterns are distributed across multiple levels (M*1st level and M*2nd level), then routing flexibility is improved, but the number of wiring patterns increases and access points are reduced
Solution Approach 1:
The patent concentrates pin patterns from a two-level distribution (M*1st level and M*2nd level) into a single level (M*1st level), effectively reducing the dimensional spread of pin placement. This concentration in one metallization level reduces the number of required wiring patterns and via connections while maintaining routing flexibility through optimized track arrangements along cell boundaries.
2Device complexity
If pin patterns are concentrated in the M*1st level along fewer tracks, then the number of wiring patterns in the M*2nd level is reduced, but routing options may be limited
Solution Approach 1:
The patent segments the cell boundary into four sides (first side, second side, third side, fourth side) and assigns different pin patterns to different sides. Each pin pattern is arranged along tracks extending in specific directions (first direction or second direction) perpendicular to the respective side. This segmentation allows pins to be accessed from multiple directions while maintaining concentration in the M*1st level, thus preserving routing options despite reduced wiring patterns.
Solution Approach 2:
The patent applies different track arrangements and pin pattern configurations to different sides of the cell. Pins on opposite sides may be arranged along tracks extending in opposite directions, optimizing local routing paths for each side while maintaining overall concentration in the M*1st level. This local optimization preserves routing flexibility without requiring additional wiring patterns.
3Ease of manufacture
If conventional design rule sets are used, then manufacturing process compatibility is maintained, but the 'stacked 2AP pattern' issue restricts via-based connections
Solution Approach 1:
The patent proactively prevents the formation of the problematic 'stacked 2AP pattern' configuration by carefully designing pin pattern placements and track arrangements. By concentrating pins in the M*1st level and arranging them along specific tracks that extend perpendicular to cell sides, the design inherently avoids creating stacked access point patterns that would restrict via-based connections, thus maintaining ease of operation while preserving process compatibility.
Data Source
AI summary
A method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.