Semiconductor Device Pin Structure for Miniaturization and Stress Relief
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing chip size, complexity in manufacturing processes, and risk of fracturing due to stress concentration at pin boundaries, which limits the miniaturization and reliability of semiconductor devices.
Innovation Solution
A semiconductor device configuration featuring a first insulating circuit substrate with a semiconductor chip and a second insulating circuit substrate having through-holes with conductive members, where first pins with a columnar part connected to control electrodes and a wider head part are inserted, reducing pin intervals and stress susceptibility, and allowing for shorter internal wiring distances and smaller chip sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the intervals between lead pins on the chip are made the same as the intervals between other ends of lead pins, then the lead pin structure is simplified, but the chip size cannot be reduced
Solution Approach 1:
The patent applies asymmetry by making the interval between lead pins on the chip different from the interval between other ends of lead pins. Specifically, the chip-side interval is designed to be smaller than the external interval, allowing the chip to be smaller while maintaining proper lead pin spacing for external connections.
2Strength
If the opening area of the opening in the solder resist layer widens toward the inner direction of the substrate, then the pin attachment strength is improved, but the manufacturing process becomes complex
Solution Approach 1:
The patent extracts the complex opening structure from the solder resist layer and replaces it with a simplified approach using a recess in the substrate and a conductive layer filling. This maintains the pin attachment strength while significantly simplifying the manufacturing process by eliminating the need for complex opening formation and widening operations in the solder resist layer.
3Device complexity
If the boundary between the nail-shaped head of the conductive pin and the rod-shaped part is exposed, then the pin structure is simplified, but stress concentration occurs at the boundary causing fracture risk
Solution Approach 1:
The patent applies beforehand cushioning by providing a recess in the substrate that receives and cushions the conductive pin. The recess walls surround the pin, preventing lateral stress from concentrating at the boundary between the head and rod-shaped parts. This protective structure is built in advance during substrate fabrication, ensuring the pin is protected before stress is applied during operation.
4Manufacturing precision
If the head part of the pin is made wider than the through-hole inner diameter, then the pin positioning accuracy is improved, but the device installation area increases
Solution Approach 1:
The patent applies the nested doll principle by nesting the pin's head part within the recess structure. The head part is positioned within the recess boundaries, using the recess walls for positioning rather than requiring the head to extend beyond the through-hole. This allows accurate positioning while containing the pin structure within a compact area, reducing the overall device installation footprint.
Data Source
AI summary
The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.