Semiconductor Pipe Channel Protection via Dummy Gate Etch Stop
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Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices face damage to the pipe channel layer and surrounding memory layer when forming slits to separate word lines, and the memory layer's insufficient thickness can lead to charge trapping during programming or erasing, affecting the threshold voltage of the pipe transistor.
Innovation Solution
A semiconductor device with a dummy pipe gate formed of non-conductive material contacting the top surface of the pipe channel layer, which serves as an etch stop layer during slit formation, preventing damage to the pipe channel and memory layers, and an additional insulating layer is formed to enhance the gate insulating layer's thickness, preventing charge trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a slit is formed to separate source side word line and drain side word line, then word line separation is achieved, but pipe channel layer and memory layer are damaged
Solution Approach 1:
A dummy pipe gate structure is formed over the pipe channel layer before slit formation. This dummy structure serves as a protective layer that prevents damage to the pipe channel layer and memory layer during subsequent slit etching processes. The dummy pipe gate is formed in advance to provide mechanical support and protection during the manufacturing process.
Solution Approach 2:
The dummy pipe gate acts as an intermediary protective layer between the etching process and the sensitive pipe channel layer/memory layer. This intermediate structure absorbs the mechanical stress and damage that would otherwise be inflicted on the underlying layers during slit formation, thereby protecting the critical functional layers.
2Productivity
If memory layer thickness is reduced, then device integration is improved, but charge trapping occurs during program or erase operation
Solution Approach 1:
The gate insulating layer is segmented into multiple distinct layers: a first gate insulating layer directly on the pipe channel layer, and a second gate insulating layer on top of the first. This segmentation allows each layer to have optimized thickness and material properties, with the combined structure providing sufficient total thickness to prevent charge trapping while maintaining high integration density.
Solution Approach 2:
The thickness and material composition of the gate insulating layer are optimized through parameter adjustment. By forming a multi-layer gate insulating structure with specific thickness ratios and material selections, the device achieves both thin overall dimensions for integration and sufficient insulating thickness to prevent charge trapping during programming and erasing operations.
Data Source
AI summary
A semiconductor device includes vertical channel layers, a pipe channel layer coupling bottoms of the vertical channel layers, a pipe gate contacting a bottom surface and side surfaces of the pipe channel layer, and a dummy pipe gate formed of a non-conductive material and contacting a top surface of the pipe channel layer.