Semiconductor Pitch Halving via Dummy Spacer Formation
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Solution Overview
Problem
As semiconductor technologies progress to smaller feature sizes, photolithography technologies face difficulties in forming well-defined pitches, necessitating a method to reduce pitch without changing the photolithography technology.
Innovation Solution
A method involving multiple layers and photomasks, including mask layers, dummy layers, spacer layers, and etching processes, is used to halve the pitch size, allowing for smaller feature sizes while maintaining the existing photolithography technology, utilizing techniques like chemical vapor deposition and atomic layer deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If photolithography technology is used to form smaller features, then feature size decreases, but pitch definition becomes difficult
Solution Approach 1:
The pitch halving process segments the patterning into multiple steps: first forming dummy features at the original pitch, then creating spacers around each dummy feature, and finally using the spacers as new features while removing the dummies. This segmentation allows achieving half-pitch features through sequential processing rather than direct single-step patterning, resolving the pitch definition difficulty.
Solution Approach 2:
The invention transitions from two-dimensional planar patterning to three-dimensional spacer formation. By depositing conformal spacer layers around dummy features and then anisotropically etching, the process creates features in the vertical dimension that translate to improved horizontal pitch control, effectively halving the pitch while maintaining photolithography capabilities.
2Productivity
If pitch is reduced to increase functional density, then functional density increases, but photolithography capability is exceeded
Solution Approach 1:
The process performs preliminary actions by first forming dummy features at the current photolithography-limited pitch, then adding spacer layers that will become the final features. This preliminary patterning followed by spacer formation allows achieving smaller pitches without pushing the photolithography system beyond its capabilities, thereby increasing functional density while maintaining manufacturing precision.
Solution Approach 2:
Dummy features serve as intermediaries in the pitch halving process. They are formed at the original pitch using standard photolithography, then spacers are deposited around them. The dummy features are subsequently removed, leaving only the spacer features at half the original pitch. This intermediary approach enables pitch reduction without exceeding photolithography limits.
3Length of moving object
If multiple photomasks are used to reduce pitch, then pitch reduction is achieved, but process complexity increases
Solution Approach 1:
The invention merges multiple functions into fewer photomask steps. Instead of using separate photomasks for each feature layer, the process uses self-aligned spacer formation where the dummy features automatically define the position of the final features. This merging of alignment functions into the spacer deposition process reduces the number of photomasks needed while achieving pitch halving.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the smallest possible pitch size by half, enabling higher packing density and smaller feature sizes without altering the photolithography technology, and can form features of varying sizes in the same process step using fewer photomasks.
Implementation Method 1
utilizing techniques like chemical vapor deposition and atomic layer deposition
Implementation Method 2
utilizing techniques like chemical vapor deposition and atomic layer deposition
Data Source
AI summary
The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.


