Semiconductor Pitch Multiplication via Spacer Formation
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Solution Overview
Problem
Current photolithography techniques struggle to achieve sufficient etching resistance and resolution for microfabrication and high densification of semiconductor memories, as thinner photoresists alone cannot meet the demand for smaller feature sizes below the lithography resolution limit.
Innovation Solution
The method involves using a hard mask, such as a silicon nitride film, to transfer a core pattern and form spacers, followed by selective elimination of the spacers to create patterns with pitches smaller than the lithography resolution limit, employing techniques like SADP and LELE to achieve finer island patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If thinner photoresist is used to improve resolution, then the resolution is improved, but the etching resistance deteriorates
Solution Approach 1:
The patent divides the patterning process into multiple stages: first forming a core pattern, then forming spacers on the core pattern, and finally forming gap patterns between the spacers. This segmentation allows each stage to use optimized photoresist thickness for its specific purpose, with the final pattern resolution determined by the spacer width rather than the initial photoresist thickness.
Solution Approach 2:
The patent introduces spacers as an intermediary structure between the core pattern and the final gap pattern. The spacers serve as a mediating element that transfers the pattern from the core to the final structure, enabling resolution multiplication while the hard mask provides the necessary etching resistance for the underlying substrate.
2Manufacturing precision
If lithography resolution is improved to meet microfabrication demand, then the feature size is reduced, but the pace is not fast enough to meet the demand for high densification
Solution Approach 1:
The patent transitions from direct lateral patterning to a multi-dimensional approach by forming vertical spacer structures on core patterns. This dimensional transition allows the final pitch to be determined by spacer thickness (vertical dimension control) rather than direct lithographic resolution, effectively multiplying the pattern density by a factor of 2-4 times beyond the lithography limit.
3Manufacturing precision
If SADP technique is used to form patterns with smaller pitch, then the pitch is reduced to half, but the process complexity increases
Solution Approach 1:
The patent merges the core pattern formation and gap pattern formation into a unified self-aligned process. The spacers are formed directly on the core patterns, and the gap patterns are automatically positioned between the spacers, eliminating the need for separate alignment steps and reducing process complexity despite achieving pitch multiplication.
Data Source
AI summary
Disclosed herein is a manufacturing method of a semiconductor device that includes forming first and second layers over an underlying martial such that the first layer is between the underlying material and the second layer, forming a third layer over the second layer, forming first and second core portions apart from each other over the third layer, forming a gap portion between the first and the second core portions; and removing the second and the third layers by using the first and the second core portions and the gap portion as a mask to expose a part of the first layer.