Semiconductor Pitch Reduction via Ion Implantation and Selective Etching
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Solution Overview
Problem
Conventional methods for reducing the pitch of integrated circuits, such as multiple exposure and patterning schemes, are complex and prone to defects due to the need for multiple layer stacks and numerous etching steps, limiting the ability to increase circuit density effectively.
Innovation Solution
A method involving ion implantation and selective etching of polysilicon layers using a TMAH wet etch process, where ion-implanted features are protected from etching, allowing for precise control and reduction of pitch without the complexity of multiple layer stacks and etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple exposure and patterning schemes are used to reduce pitch, then pitch reduction is achieved, but process complexity and defect rate increase
Solution Approach 1:
The patent segments the pitch reduction process into two distinct stages: first forming a sacrificial mandrel pattern at the target pitch, then using it to deposit and pattern the final pitch-reduced features. This segmentation allows each stage to be optimized independently, achieving pitch reduction without requiring complex multi-layer stacks and multiple etching steps.
Solution Approach 2:
The patent introduces a sacrificial mandrel as an intermediary structure that enables pitch reduction. The mandrel is formed at the target pitch, serves as a template for depositing the final features, and is subsequently removed. This intermediary approach simplifies the overall process by providing a straightforward mechanism to achieve pitch reduction without complex patterning schemes.
2Manufacturing precision
If multiple exposure and patterning schemes are used to reduce pitch, then pitch reduction is achieved, but defect rate increases
Solution Approach 1:
By segmenting the process into mandrel formation followed by simple deposition and removal, the patent eliminates the need for multiple exposure and etching steps that create defects. Each step is simpler and more controllable, reducing the cumulative defect rate while achieving the desired pitch reduction.
Solution Approach 2:
The patent converts the potential harm of using complex multi-step processes into a benefit by adopting a simpler approach. The sacrificial mandrel method transforms what would be a complex patterning challenge into a straightforward deposition and removal sequence, thereby reducing defects while achieving pitch reduction.
3Ease of manufacture
If conventional photolithography is used, then manufacturing process is simple, but minimum pitch is limited by resolution capability
Solution Approach 1:
The patent moves the pitch reduction problem from the photolithographic patterning dimension to the deposition dimension. Instead of relying on photolithography resolution to define the final pitch, the method uses physical deposition processes that can achieve finer features, effectively solving the pitch limitation while keeping the overall process simple.
Solution Approach 2:
The patent performs preliminary action by forming the sacrificial mandrel structure at the target pitch before depositing the final features. This preliminary mandrel formation enables subsequent simpler deposition steps to achieve the final pitch-reduced structure, bypassing the photolithography resolution limit while maintaining process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process of reducing integrated circuit pitch, enhancing control and reliability while minimizing defects, thereby increasing circuit density and functionality.
Implementation Method 1
A method involving ion implantation and selective etching of polysilicon layers using a TMAH wet etch process
Implementation Method 2
A method involving ion implantation and selective etching of polysilicon layers
Data Source
AI summary
A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.