Semiconductor Pixel Region Transistor Arrangement for Signal Processing
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Solution Overview
Problem
Conventional solid-state imaging elements with a single photoelectric conversion element within each pixel region have limited signal processing capacity due to light shielding, leading to increased wire length and capacitance when two photoelectric conversion elements are used, which hampers high-speed focus adjustment and signal processing.
Innovation Solution
A semiconductor device with multiple pixel regions, each containing two photoelectric conversion elements, two floating capacitance regions, and a first transistor arranged between the floating capacitance regions to reduce wire length and capacitance by sharing amplification and reset transistors within the pixel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two photoelectric conversion elements are arranged within one pixel region to increase signal processing capacity, then the amount of signals that can be processed at one time is substantially doubled, but the wire length connecting each photoelectric conversion element to the transistor becomes unreasonably long, causing increased wire capacitance
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration. The first photoelectric conversion element is positioned above the second element in the vertical dimension, while both connect to the same transistor through vertically stacked transfer transistors. This spatial reorganization dramatically reduces the horizontal wire length between photoelectric conversion elements and the shared transistor, thereby reducing wire capacitance while maintaining dual-element signal processing capacity.
2Ease of operation
If another transistor is arranged in a region away from the photoelectric conversion element to receive electric signals, then the transistor can be properly positioned for signal reception, but the wire connecting the photoelectric conversion element and the transistor becomes excessively long
Solution Approach 1:
The patent merges the functionality of multiple transistors into a compact stacked configuration. The first transfer transistor and second transfer transistor are vertically stacked and share common connection nodes, allowing both photoelectric conversion elements to connect to the same transistor circuitry through minimal wire length. This consolidation eliminates the need for separate transistor placements while maintaining proper signal reception capabilities.
3Ease of operation
If a light shielding film is used to shield half of the light incident region for focus adjustment, then focus adjustment can be performed in one eye's field of vision, but only a small amount of signals can be processed at one time
Solution Approach 1:
The patent segments the light incident region into two distinct photoelectric conversion elements positioned at different vertical levels. Each element can independently receive light and generate signals, with the first element positioned above the second element. This segmentation allows both elements to simultaneously process signals without the need for light shielding, thereby doubling the signal processing capacity while maintaining focus adjustment capabilities through the stereoscopic arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces wire length and capacitance, enabling faster signal processing and improved focus adjustment capabilities by minimizing the length of connecting wires and enhancing layout efficiency within the semiconductor device.
Implementation Method 1
two photoelectric conversion elements, two floating capacitance regions... each of the two photoelectric conversion elements... takes out and accumulates an electric signal output from the photoelectric conversion element
Data Source
AI summary
A plurality of pixel regions are aligned in a matrix in a semiconductor substrate, and each of the plurality of pixel regions includes an active region, two photoelectric conversion elements, two floating capacitance regions, and a first transistor. Each of the plurality of pixel regions includes two transfer transistors each having each of the two photoelectric conversion elements and each of the two floating capacitance regions. The first transistor is arranged within the pixel region, between one floating capacitance region and the other floating capacitance region of the two floating capacitance regions with respect to a direction in which the one floating capacitance region and the other floating capacitance region are aligned.