Semiconductor Construct Placement for Thermal Stress Reduction
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Solution Overview
Problem
Conventional semiconductor devices face damage due to thermal stress in junction portions of second semiconductor constructs caused by differences in thermal expansion coefficients between semiconductor substrates and insulating layers.
Innovation Solution
All jointing portions of the second semiconductor constructs are disposed within the region corresponding to the first semiconductor construct, minimizing the impact of thermal expansion and contraction of the insulating layer and reducing the difference in thermal expansion coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If jointing portions of second semiconductor constructs are disposed in a region corresponding to the insulating layer on the periphery of the first semiconductor construct, then the area utilization of the base plate is improved, but the reliability deteriorates due to thermal stress damage
Solution Approach 1:
The patent applies local quality by creating distinct placement zones with different thermal characteristics. The region corresponding to the first semiconductor construct has similar thermal expansion properties to the second semiconductor constructs, while the region corresponding to the insulating layer has different thermal expansion properties. By localizing the jointing portions to the appropriate zone, the patent optimizes both area utilization and thermal stress resistance.
Solution Approach 2:
The patent converts the potentially harmful thermal expansion difference into a beneficial design criterion. Instead of treating thermal expansion difference as a problem to be eliminated, the patent uses it as a basis for zonal placement strategy. The harmful thermal stress is converted into a useful design parameter that guides the optimal positioning of jointing portions.
2Area of stationary object
If jointing portions are disposed in regions with different thermal expansion coefficients, then area utilization is improved, but the thermal stress resistance deteriorates
Solution Approach 1:
The patent creates spatially differentiated zones based on thermal expansion characteristics. The first zone (corresponding to the first semiconductor construct) has thermal expansion properties matched to the second semiconductor constructs, while the second zone (corresponding to the insulating layer) has different thermal expansion properties. This local quality differentiation allows optimal placement of jointing portions to minimize thermal stress while maintaining area utilization.
Solution Approach 2:
The patent transforms the harmful thermal expansion coefficient difference into a useful design parameter for zonal placement. By recognizing and utilizing the thermal expansion characteristics of different regions, the patent converts what would be a source of stress into a guiding principle for optimal component placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents damage from thermal stress in the junction portions of the second semiconductor constructs by aligning their placement with the first semiconductor construct, ensuring stable thermal expansion and contraction.
Implementation Method 1
there is a problem that the other part of the junction portion of the second semiconductor construct, especially, might be damaged due to thermal stress caused from a difference of thermal expansion coefficients between the semiconductor substrate (silicon) of the second semiconductor construct and the insulating layer (resin)
Data Source
AI summary
A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating layer. Upper layer wiring lines are provided on the upper layer insulating film so that the upper layer wiring line is electrically connected to the external connection electrode. A second semiconductor construct is joined to and installed on connection pad portions. All jointing portions of the second semiconductor construct for the connection pad portions of the upper layer wiring lines are disposed in a region corresponding to the first semiconductor construct.


