Semiconductor Placement and Routing Algorithm Optimization
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Solution Overview
Problem
Existing Electronic Design Automation (EDA) schemes struggle to optimize the placement and routing of semiconductor devices as the degree of integration increases, leading to inefficiencies in design and increased wire length.
Innovation Solution
A design method and system that utilize multiple algorithms to optimize the placement of micro-cells and standard cells, reducing deadspace, and design routing paths that minimize wire length by recognizing avoidance targets and adjusting node positions to form right-angle paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing EDA schemes are used for placement and routing, then the design process can be completed, but the wire length increases and design efficiency decreases as integration degree increases
Solution Approach 1:
The patent segments the routing calculation into two distinct algorithms: a first algorithm for initial routing path calculation and a second algorithm for optimized routing path calculation. This segmentation allows each algorithm to specialize in different aspects of routing optimization, thereby reducing overall wire length while maintaining design efficiency.
Solution Approach 2:
The patent implements a dynamic verification mechanism where the second algorithm's results are used to verify and potentially optimize the first algorithm's results. This dynamic approach allows the system to adapt and improve routing paths based on comparative evaluation, reducing wire length without significantly increasing design time.
2Productivity
If multiple algorithms are used for placement and routing optimization, then wire length is reduced and design efficiency improves, but the computational complexity increases
Solution Approach 1:
The patent applies partial action by using the second algorithm selectively - only when the verification condition is met. The second algorithm does not always execute but rather conditionally optimizes based on the first algorithm's results. This reduces the overall computational burden while still achieving routing optimization when beneficial.
Solution Approach 2:
The patent implements a feedback mechanism where the second algorithm's results feed back into the verification process of the first algorithm's results. This feedback loop allows the system to learn from the second algorithm's optimizations and apply them selectively, reducing complexity while maintaining improved design efficiency.
3Productivity
If semiconductor devices with higher connection frequency are placed closer together, then routing efficiency improves, but placement complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-identifying and prioritizing devices with higher connection frequencies before the actual placement process. This preliminary identification allows the placement algorithm to focus computational resources on critical devices first, improving routing efficiency without requiring complex real-time calculations during placement.
Data Source
AI summary
A design method for placing and routing a semiconductor device in a computer system includes placing, by the computer system, a plurality of semiconductor devices in a design region, calculating and evaluating, by the computer system, a routing path between the plurality of semiconductor devices, based on a first algorithm, calculating, by the computer system, the routing path between the plurality of semiconductor devices based on a result calculated through the first algorithm and a second algorithm, based on an evaluation result, and comparing the result calculated through the first algorithm with a result calculated through the second algorithm, and verifying the result calculated through the first algorithm, based on a comparison result.