Semiconductor Planar Coating with Selective Crosslink Rinse
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Solution Overview
Problem
As semiconductor devices shrink in size, controlling variations in fabrication processes becomes more challenging, leading to issues with planarity and uniformity, which can result in reduced productivity and reliability in semiconductor manufacturing.
Innovation Solution
A multilayer coating process using spin-on carbon materials with crosslinking capabilities, combined with a solvent rinse operation, is employed to achieve planarity and uniformity on patterned features with varying gap sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If device dimensions are reduced to meet consumer demand for smaller electronic devices, then device size decreases, but planarity and uniformity control become more difficult
Solution Approach 1:
The coating process is divided into multiple sequential layers (first layer, second layer, third layer) with different functions. The first layer addresses planarity, the second layer enhances uniformity through selective crosslinking, and the third layer provides final coating completion. This segmentation allows each layer to optimize for its specific purpose without compromising overall device miniaturization goals.
Solution Approach 2:
The patent applies selective crosslinking to the second layer in specific regions (first region versus second region) based on gap sizes between patterned features. Areas with smaller gaps receive different treatment than areas with larger gaps, creating local quality variations that compensate for topography biases and achieve uniform coating thickness across the entire substrate despite varying feature densities.
2Device complexity
If conventional single-layer coating processes are used on patterned features with varying gap sizes, then process simplicity is maintained, but topography biases result in non-uniform coating thickness
Solution Approach 1:
The patent uses a composite multilayer coating structure where each layer has distinct material properties and functions. The first layer provides planarization, the second layer with crosslinking capabilities provides uniformity control, and the third layer completes the coating. This composite approach achieves coating uniformity on complex topographies while maintaining a systematic, scalable process.
Solution Approach 2:
The first layer is applied and processed (including crosslinking) before the second layer is deposited. This preliminary action of planarizing the surface with the first layer creates a more uniform base for subsequent layers, preventing topography biases from propagating through the entire coating structure.
3Volume of moving object
If device dimensions are reduced, then device size decreases, but etch control and substrate damage risks increase
Solution Approach 1:
The multilayer coating structure with crosslinked regions serves as a protective cushion before subsequent fabrication processes. The crosslinked second layer provides mechanical support and protection to the underlying substrate and patterned features, reducing the risk of damage during etching and other processing steps that follow device fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayer coating process effectively compensates for topography biases, resulting in a planar and uniform coating across different areas, thereby improving the reliability and productivity of semiconductor device manufacturing.
Implementation Method 1
forming a first planarizing layer over a patterned surface of a substrate
Implementation Method 2
the first planarizing layer includes a spin-on carbon and an acid generator, and the acid generator generates an acid
Implementation Method 3
the acid generator generates an acid in response to heating or irradiation with actinic radiation
Implementation Method 4
the acid diffuses from the first layer to the second layer
Implementation Method 5
crosslinking a portion of the second planarizing material
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.