Semiconductor Planarization via Dielectric Etching and Polishing
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Solution Overview
Problem
The 3D integration of semiconductor structures often results in poor adhesion due to rough, non-planar surfaces, leading to undesirable separation during subsequent processes.
Innovation Solution
A method involving the formation of a dielectric layer over a non-planar surface, followed by etching and polishing to create a planarized surface, which allows for the attachment of additional semiconductor structures with improved bond strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor devices are formed using conventional processes, then device functionality is achieved, but the surface becomes rough and non-planar
Solution Approach 1:
The surface planarization process is divided into multiple discrete steps: depositing a first dielectric layer, forming a masking layer with patterned openings, selectively etching exposed regions, and performing chemical mechanical polishing. This segmented approach allows each step to be optimized independently, achieving both device functionality and surface planarity.
Solution Approach 2:
Dielectric layers and masking patterns are formed in advance before the final attachment process. The masking layer is patterned with openings that predefine the regions to be etched, and the dielectric layers are deposited beforehand to provide a foundation for subsequent planarization steps, enabling efficient surface preparation.
2Productivity
If a semiconductor structure is attached to a rough non-planar surface, then 3D integration is achieved, but adhesion quality deteriorates
Solution Approach 1:
The surface is planarized through etching and polishing operations before the attachment process occurs. This preliminary preparation ensures that when semiconductor structures are attached, they bond to a smooth, planar surface, guaranteeing high adhesion quality while maintaining 3D integration productivity.
Solution Approach 2:
Dielectric layers serve as intermediary materials between the rough processed semiconductor structure and the structure to be attached. These dielectric layers fill in surface irregularities and provide a planar bonding surface, mediating between the non-planar underlying structure and the requirement for high-quality adhesion.
3Manufacturing precision
If additional processing steps are added to planarize the surface, then surface smoothness is improved, but process complexity increases
Solution Approach 1:
Multiple functions are merged into the dielectric layer system: the dielectric layers provide electrical insulation, mechanical support, and serve as a planarization substrate. The masking layer combines patterning and protection functions. This merging reduces the need for separate dedicated planarization structures, managing process complexity while achieving surface smoothness.
Solution Approach 2:
The physical and chemical parameters of the dielectric layers are optimized to enable effective planarization. The dielectric materials are selected with appropriate etch selectivity, mechanical properties, and deposition characteristics that facilitate surface smoothing through controlled etching and polishing, achieving surface smoothness through parameter optimization rather than additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the planarity of semiconductor surfaces, ensuring strong and reliable attachment of semiconductor structures, reducing the likelihood of separation during handling and further processing.
Implementation Method 1
A surface of the dielectric layer on a side thereof opposite the non-planar surface of the processed semiconductor structure may be planarized to form a planarized surface. Planarizing the surface of the dielectric layer may include etching regions of the dielectric layer exposed through the plurality of mask openings
Implementation Method 2
polishing the surface of the dielectric layer after the etching of the regions of the dielectric layer
Data Source
AI summary
The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.