Semiconductor Device Fabrication with Planarized Interlayer Insulating Films
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The variation in gate electrode heights due to different thicknesses of gate insulating layers in semiconductor devices introduces weak points, degrading the reliability of the semiconductor device.
Innovation Solution
A method for fabricating semiconductor devices involves forming transistors with varying threshold voltages by creating regions with different interlayer insulating film heights, followed by planarization to ensure uniform upper surfaces, thereby reducing height variations and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistors with different threshold voltages are fabricated by varying gate insulating layer thickness, then transistor functionality is improved, but gate electrode height variation increases
Solution Approach 1:
The patent applies local quality by forming different thicknesses of interlayer insulating films (first, second, and third interlayer insulating films) in different regions of the substrate. This allows each region to have customized gate electrode heights tailored to specific threshold voltage requirements while maintaining overall device functionality. The first interlayer insulating film is formed thicker in regions requiring higher threshold voltages, while the second and third films are formed thinner in regions requiring lower threshold voltages.
2Adaptability or versatility
If gate insulating layer thickness is varied to control threshold voltage, then transistor performance is improved, but device reliability deteriorates
Solution Approach 1:
The patent implements parameter changes by systematically varying the thickness of interlayer insulating films as a key geometric parameter. By controlling the thickness parameters of the first, second, and third interlayer insulating films differently across substrate regions, the invention achieves precise threshold voltage control while maintaining manufacturing reliability through a structured, parameter-based fabrication approach.
3Manufacturing precision
If planarization is performed to reduce height variation, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming interlayer insulating films with different thicknesses in specific regions before completing the gate electrode formation process. This preliminary structuring of the substrate with varied interlayer film thicknesses allows for controlled threshold voltage implementation while managing process complexity through systematic, staged fabrication steps rather than attempting post-formation height adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the variation in gate electrode heights, enhancing the reliability and performance of semiconductor devices by minimizing weak points and optimizing threshold voltage control.
Implementation Method 1
planarizing the first region, the second region, and the third region, wherein before planarizing the first region, the second region, and the third region, a first difference of height between an upper surface of the first region and an upper surface of the second region corresponds to a first value, and wherein after planarizing the first region, the second region, and the third region, a second difference of height between an upper surface of a planarized first region and an upper surface of a planarized second region corresponds to a second value, and wherein the first value is greater than the second value
Data Source
AI summary
A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.