Semiconductor Planarization Process for Loading Effect Mitigation
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Solution Overview
Problem
The scaling of semiconductor devices exacerbates the loading effect in planarization processes due to significant differences in pattern density and height between regions, leading to poor surface uniformity, particularly in DRAM technology nodes smaller than 14 nm, where regions with lower pattern density are excessively removed, causing damage.
Innovation Solution
A semiconductor process that involves forming regions with different pattern densities, applying dielectric layers with varying polishing and etching rates, and performing sequential planarization and etching processes to achieve surface uniformity without additional photolithographic steps, using organic dielectric layers with self-planarization properties to mitigate the loading effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planarization process is used on substrates with high pattern density differences, then the process can be completed with standard procedures, but the surface uniformity deteriorates and regions with lower pattern density are excessively removed
Solution Approach 1:
The patent applies preliminary planarization processes before the final planarization step. Specifically, a first planarization process is performed to reduce the height difference between high-density and low-density regions, followed by a second planarization process to achieve the final surface uniformity. This preliminary action prevents the loading effect from causing excessive removal in low-density regions during the main planarization step.
2Manufacturing precision
If multiple planarization processes are performed to improve surface uniformity, then the planarization quality improves, but the process complexity and cost increase
Solution Approach 1:
The patent segments the planarization process into multiple distinct steps: a first planarization process using specific conditions to address high-density regions, and a second planarization process to finalize the surface. Each segment targets specific aspects of the surface uniformity problem, allowing complex surface profiles to be managed through simpler, targeted process steps rather than a single complex process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process effectively reduces surface roughness to less than 3% and achieves even planarization across regions with varying pattern densities, improving the uniformity and reducing damage during the planarization step.
Implementation Method 1
Multiple planarization processes, such as a chemical mechanical planarization (CMP) or an etch back process, should be performed during the manufacture of semiconductor integrated circuit
Data Source
AI summary
A semiconductor process for improving loading effects in planarization is provided including steps of forming multiple first protruding patterns on a first region and a second region of a substrate, wherein the pattern density of the first protruding patterns in the first region is larger than the one in the second region, forming a first dielectric layer on the substrate and the first protruding patterns, wherein the first dielectric layer includes multiple second protruding patterns corresponding to the first protruding patterns below, forming a second dielectric layer on the first dielectric layer, performing a first planarization process to remove parts of the second dielectric layer, so that the top surface of the second protruding patterns are exposed, performing an etch process to remove the second protruding patterns of the first dielectric layer, removing the remaining second dielectric layer, and performing another planarization process to the first dielectric layer.