Semiconductor Planarization Using Peripheral Conductive Pads
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is achieving uniform planarization between peripheral and array regions, as non-uniform thickness of filler materials can lead to excessive material removal during chemical-mechanical planarization (CMP), causing defects such as contamination, performance failures, and electrical shorts.
Innovation Solution
The implementation of conductive pads with a larger surface area in the peripheral region, which provides improved control and tolerance during planarization, using these pads and spacer materials as stop materials to ensure uniform material removal across both regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single CMP operation is performed on both peripheral and array regions, then manufacturing efficiency is improved, but planarization uniformity deteriorates due to non-uniform filler material thickness
Solution Approach 1:
The patent applies local quality by creating conductive pads with larger surface area specifically in the peripheral region, while maintaining normal feature sizes in the array region. This local structural modification allows the peripheral region to tolerate non-uniform filler material thickness during CMP operations, as the larger pad area provides a buffer zone that prevents excessive material removal. The array region retains its precise original structure for high-density memory cells, thus resolving the contradiction between manufacturing efficiency and planarization uniformity.
2Ease of manufacture
If filler material thickness is not controlled uniformly, then ease of manufacture is improved, but device reliability deteriorates due to material removal defects
Solution Approach 1:
The patent implements beforehand cushioning by introducing conductive pads with enlarged surface area in the peripheral region prior to the CMP operation. These pads serve as a cushioning structure that compensates for potential over-removal of filler material. Even if the CMP process removes excessive material in areas with non-uniform filler thickness, the larger pad area ensures that underlying structures remain protected and functional, thus preventing device failures while maintaining manufacturing simplicity.
3Manufacturing precision
If CMP removes excessive material in array region, then planarization is improved, but harmful effects increase due to contamination and electrical shorts
Solution Approach 1:
The patent uses conductive pads as intermediary structures between the CMP process and the underlying array features. These pads act as a protective mediator that absorbs the harmful effects of excessive material removal. During CMP, the larger pad area in the peripheral region serves as a buffer zone that prevents the abrasive process from directly impacting the array region features, thereby preventing contamination and electrical shorts while still achieving the desired planarization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances planarization uniformity, reducing the risk of over- or under-removal of material, thereby minimizing defects and performance failures in semiconductor devices.
Implementation Method 1
both the peripheral region and array region are planarized through a single CMP operation
Data Source
AI summary
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.