Semiconductor Device Plate Portion Asymmetric Width
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, the aspect ratio of slits in the stacked body leads to varying resistance values across electrode layers, making it difficult to pattern them perpendicularly from the upper surface to the substrate, resulting in wider planar surfaces at the lower layer and narrower at the upper layer, causing resistance differences.
Innovation Solution
A semiconductor device design with a stacked body comprising multiple electrode layers, a columnar portion with a semiconductor body and memory film, and a plate portion with a plate conductor and sidewall insulating film, where the plate portion's width varies along the stacking direction to minimize resistance differences across the electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the slit is patterned perpendicularly from the upper surface to the substrate, then the manufacturing process is simple, but the planar surface area of electrode layers becomes non-uniform causing resistance value differences
Solution Approach 1:
The patent applies asymmetry by making the slit width in the minor-axis direction non-uniform along the stacking direction. Specifically, the slit width is set to be larger in the lower layer portion (near substrate) and smaller in the upper layer portion (near upper surface). This asymmetric width distribution compensates for the natural widening of electrode layers in lower layers, maintaining uniform planar surface area and consistent resistance values across all electrode layers.
Solution Approach 2:
The patent changes the geometric parameter of the slit (width in minor-axis direction) along the stacking direction to control the planar surface area of electrode layers. By varying the slit width parameter from larger at the bottom to smaller at the top, the patent maintains uniform resistance characteristics across electrode layers with different positions in the stacked body.
2Manufacturing precision
If the slit width is uniform throughout the stacked body, then the electrode layer planar surface area becomes non-uniform, but if the slit width varies, then manufacturing complexity increases
Solution Approach 1:
The patent introduces asymmetric slit width variation along the stacking direction to compensate for the symmetric expansion of electrode layers. The slit is designed with larger width in lower layers and smaller width in upper layers, creating an asymmetric geometry that balances the overall resistance characteristics across all electrode layers.
Solution Approach 2:
The patent applies local quality by giving different widths to the slit at different positions along the stacking direction. The slit width is locally adjusted - larger near the substrate and smaller near the upper surface - to match the local planar surface area requirements of electrode layers at different heights, thereby achieving uniform resistance characteristics throughout the device.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a substrate; a stacked body; a columnar portion; and a plate portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers include first to third electrode layers. The first electrode layer is most proximal to the substrate. The second electrode layer is most distal to the substrate. The columnar portion and the plate portion are provided inside the stacked body. The plate portion extends along the stacking direction of the stacked body and along a first direction orthogonal to the stacking direction. The plate portion includes first to third portions. The third portion is provided between the first portion and the second portion. Widths of the first portion and the second portion along a second direction are narrower than a width of the third portion along the second direction.