Semiconductor Device Plating Mark for Solder Intrusion Prevention
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Solution Overview
Problem
The presence of position recognition holes near soldering portions in semiconductor devices can lead to solder flowing into these holes, forming vacant spaces due to surface tension, resulting in partial discharge issues and assembly reliability problems, especially when hole diameters are small.
Innovation Solution
Simultaneously forming soldering portions and marks by plating on the wiring pattern of an insulating substrate, using marks like Ni plating, resist marks, or cuts to ensure the encapsulation material fills the necessary regions without forming vacant spaces, thereby preventing partial discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If position recognition holes are provided in the wiring pattern for assembly recognition, then assembly positioning is improved, but solder may flow into the holes forming vacant spaces that cause partial discharge
Solution Approach 1:
The patent applies preliminary action by forming a plating layer on the wiring pattern before the soldering process. This plating layer is created in advance to serve as a barrier that prevents solder from flowing into the position recognition holes during subsequent soldering operations, thereby eliminating vacant spaces that would cause partial discharge while maintaining assembly positioning capability
Solution Approach 2:
The patent uses a plating layer as an intermediary substance between the solder and the position recognition holes. This intermediate layer acts as a protective barrier that allows the holes to remain open for assembly recognition while preventing solder intrusion, thus resolving the conflict between positioning functionality and insulation reliability
2Reliability
If the diameter of position recognition holes is increased to prevent solder intrusion, then partial discharge is prevented, but the region necessary for assembly is not reliably secured
Solution Approach 1:
The patent applies local quality by creating a plating layer with different properties in different regions. The plating layer is selectively formed to provide solder resistance at critical locations (around position recognition holes) while maintaining the original hole dimensions needed for assembly recognition, thus preventing partial discharge without compromising assembly region availability
3Area of stationary object
If position recognition holes with small diameter are used to secure assembly region, then assembly area is secured, but solder covers only upper portion of hole forming vacant space
Solution Approach 1:
The patent applies preliminary action by forming a plating layer on the wiring pattern before soldering. This pre-formed plating layer creates a barrier that prevents solder from flowing into small-diameter position recognition holes during the soldering process, ensuring complete filling of holes with encapsulation material and eliminating vacant spaces that would cause partial discharge
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents partial discharge and ensures reliable assembly by ensuring the encapsulation material fills the necessary regions, enhancing the dielectric strength and securing the necessary areas for assembly.
Implementation Method 1
simultaneously forming a soldering portion and a mark by plating on a wiring pattern of an insulating substrate
Implementation Method 2
When flowing into the hole, the solder is formed into a spherical or disk-like shape by its surface tension
Implementation Method 3
Failure of the encapsulation material to flow into the hole and, hence, the formation of a vacant space
Data Source
AI summary
A soldering portion (4) and a Ni plating mark (5) are simultaneously forming by plating on a wiring pattern (2) of an insulating substrate (1). A semiconductor chip (6) is mounted on the insulating substrate (1). A position of the insulating substrate (1) is recognized by the Ni plating mark (5) and a wire (7) is bonded to the semiconductor chip (6). An electrode (8) is joined to the soldering portion (4) by solder (9). The insulating substrate (1), the semiconductor chip (6), the wire (7), and the electrode (8) are encapsulated in an encapsulation material (13).